# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name: replaceRegWith_requires_copy
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr0, $vgpr0_vgpr1

    ; CHECK-LABEL: name: replaceRegWith_requires_copy
    ; CHECK: liveins: $sgpr0, $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sreg_32(s32) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY [[ICMP]](s32)
    ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
    ; CHECK-NEXT: S_ENDPGM 0
    %0:sgpr(p1) = COPY $vgpr0_vgpr1
    %1:sgpr(s32) = COPY $sgpr0
    %2:sgpr(s32) = G_CONSTANT i32 1
    %3:sreg_32(s32) = G_ICMP intpred(ne), %1, %2
    %4:sgpr(s32) = G_AND %3, %2
    G_STORE %4(s32), %0(p1) :: (store (s32), addrspace 1)
    S_ENDPGM 0
...