; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p3 -enable-subreg-liveness -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p3 -force-streaming -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p3 -force-streaming -verify-machineinstrs < %s | FileCheck %s

define <vscale x 16 x i8> @test_addsubp_i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
; CHECK-LABEL: test_addsubp_i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    addsubp z0.b, z0.b, z1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.addsubp.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @test_addsubp_i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: test_addsubp_i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    addsubp z0.h, z0.h, z1.h
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.addsubp.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
  ret <vscale x 8 x i16> %res
}

define <vscale x 4 x i32> @test_addsubp_i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) {
; CHECK-LABEL: test_addsubp_i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    addsubp z0.s, z0.s, z1.s
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.addsubp.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm)
  ret <vscale x 4 x i32> %res
}

define <vscale x 2 x i64> @test_addsubp_i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) {
; CHECK-LABEL: test_addsubp_i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    addsubp z0.d, z0.d, z1.d
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.addsubp.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm)
  ret <vscale x 2 x i64> %res
}