; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA32
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64

;; vextrins.b
define void @shufflevector_v16i8(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v16i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vextrins.b $vr0, $vr1, 240
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <16 x i8>, ptr %a
  %vb = load <16 x i8>, ptr %b
  %c = shufflevector <16 x i8> %va, <16 x i8> %vb, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 16>
  store <16 x i8> %c, ptr %res
  ret void
}

;; vextrins.h
define void @shufflevector_v8i16(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v8i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vextrins.h $vr0, $vr0, 53
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <8 x i16>, ptr %a
  %vb = load <8 x i16>, ptr %b
  %c = shufflevector <8 x i16> %va, <8 x i16> %vb, <8 x i32> <i32 0, i32 1, i32 2, i32 5, i32 4, i32 5, i32 6, i32 7>
  store <8 x i16> %c, ptr %res
  ret void
}

;; vextrins.w
define void @shufflevector_v4i32(ptr %res, ptr %a, ptr %b) nounwind {
; LA32-LABEL: shufflevector_v4i32:
; LA32:       # %bb.0: # %entry
; LA32-NEXT:    vld $vr0, $a2, 0
; LA32-NEXT:    ld.w $a1, $a1, 12
; LA32-NEXT:    vinsgr2vr.w $vr0, $a1, 0
; LA32-NEXT:    vst $vr0, $a0, 0
; LA32-NEXT:    ret
;
; LA64-LABEL: shufflevector_v4i32:
; LA64:       # %bb.0: # %entry
; LA64-NEXT:    vld $vr0, $a1, 0
; LA64-NEXT:    vld $vr1, $a2, 0
; LA64-NEXT:    vextrins.w $vr1, $vr0, 3
; LA64-NEXT:    vst $vr1, $a0, 0
; LA64-NEXT:    ret
entry:
  %va = load <4 x i32>, ptr %a
  %vb = load <4 x i32>, ptr %b
  %c = shufflevector <4 x i32> %va, <4 x i32> %vb, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
  store <4 x i32> %c, ptr %res
  ret void
}

;; vextrins.w
define void @shufflevector_v4f32(ptr %res, ptr %a, ptr %b) nounwind {
; CHECK-LABEL: shufflevector_v4f32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a2, 0
; CHECK-NEXT:    fld.s $fa1, $a1, 8
; CHECK-NEXT:    vextrins.w $vr0, $vr1, 48
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %va = load <4 x float>, ptr %a
  %vb = load <4 x float>, ptr %b
  %c = shufflevector <4 x float> %va, <4 x float> %vb, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
  store <4 x float> %c, ptr %res
  ret void
}