---
include: hipsparselt_common.yaml
include: known_bugs.yaml
include: spmm_batched_common_row.yaml

Definitions:
  - &transA_transB_range
    - { transA: N, transB: N }
    - { transA: N, transB: T }
    - { transA: T, transB: N }
    - { transA: T, transB: T }

  - &algorithm_coverage_alpha_beta_range
    - { alpha:  1.0, beta:  1.0 }
    - { alpha:  1.0, beta: -1.0 }
    - { alpha:  1.0, beta:  0.0 }
    - { alpha: -1.0, beta:  0.0 }
    - { alpha:  2.0, beta:  0.0 }
    - { alpha:  0.0, beta:  2.0 }
    - { alpha:  2.0, beta:  3.0 }

  - &alpha_beta_range
    - { alpha:  1.0, beta:  0.0 }
    - { alpha: -2.0, beta: -3.0 }
    - { alpha:  0.0, beta:  1.0 }

  - &alpha_beta_range_small
    - { alpha: 2, alphai: 2, beta: -1.0, betai: 2.0 }

Tests:
- name: spmm_batched_algorithm_real_coverage
  category: pre_checkin
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_algorithm_coverage_matrix_size_range
  transA_transB: *transA_transB_range
  alpha_beta: *algorithm_coverage_alpha_beta_range
  batch_count: [ 1, 3 ]
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

# Tests confirm no NaN propagation when alpha = 0, 2 and beta = 0. Value .NaN is converted into zero
- {name: alpha_beta_zero_NaN, category: pre_checkin, precision: *real_precisions_2b, batch_count: 1,
   function: spmm_batched, transA: N, transB: N, M: 256, N: 128, K:  64, alpha: [ .NaN, 2 ], beta: [ .NaN, 2 ] }

- name: spmm_batched_small
  category: quick
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_small_matrix_size_range
  alpha_beta: *alpha_beta_range
  transA_transB: *transA_transB_range
  batch_count: 3
  bias_vector: true
  bias_type: [f32_r, f16_r, bf16_r]
  sparse_b: [ true, false]
  alpha_vector_scaling: true
  factor_dim: [0, 1]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

- name: spmm_batched_small
  category: quick
  function:
    - spmm_batched: *hpa_half_precision
  matrix_size: *batched_small_matrix_size_range
  alpha_beta: *alpha_beta_range
  transA_transB: *transA_transB_range
  batch_count: 3
  bias_vector: true
  sparse_b: [ true, false]
  alpha_vector_scaling: true
  factor_dim: [0, 1]
  gate_residual: [true]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]
  gpu_arch: '942'

- name: spmm_batched_medium
  category: pre_checkin
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_medium_matrix_size_range
  transA_transB: *transA_transB_range
  alpha_beta: *alpha_beta_range
  batch_count: 3
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

- name: spmm_batched_large
  category: pre_checkin
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_large_matrix_size_range
  transA_transB: *transA_transB_range
  alpha_beta: *alpha_beta_range
  batch_count: 3
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

- name: spmm_batched_deepbench
  category: nightly
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_deepbench_vec
  alpha: 1.0
  beta: 0.0
  transA: N
  transB: T
  batch_count: 2
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

- name: spmm_batched_conv_resnet50_bwddata
  category: nightly
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_conv_resnet50_bwddata
  alpha: 1.0
  beta: 0.0
  transA: N
  transB: T
  batch_count: 4
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

- name: spmm_batched_conv_inception4_bwddata
  category: nightly
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_conv_inception4_bwddata
  alpha: 1.0
  beta: 0.0
  transA: N
  transB: T
  batch_count: 4
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

- name: spmm_batched_conv_ctest_fwd
  category: nightly
  function:
    - spmm_batched: *real_precisions_2b
  matrix_size: *batched_conv_ctest_fwd
  alpha: 1.0
  beta: 0.0
  transA: N
  transB: N
  batch_count: 2
  sparse_b: [ true, false]
  orderA: [R]
  orderB: [R]
  orderC: [R]
  orderD: [R]

...