; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p3 -enable-subreg-liveness -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p3 -force-streaming -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p3 -force-streaming -verify-machineinstrs < %s | FileCheck %s

define <vscale x 16 x i8> @test_svqshrn_n_s8_s16_x2(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: test_svqshrn_n_s8_s16_x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sqshrn z0.b, { z0.h, z1.h }, #8
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrn.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 8)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @test_svqshrn_n_s16_s32_x2(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) {
; CHECK-LABEL: test_svqshrn_n_s16_s32_x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sqshrn z0.h, { z0.s, z1.s }, #16
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrn.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm, i32 16)
  ret <vscale x 8 x i16> %res
}

define <vscale x 16 x i8> @test_svqshrn_n_u8_u16_x2(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: test_svqshrn_n_u8_u16_x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uqshrn z0.b, { z0.h, z1.h }, #8
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshrn.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 8)
  ret <vscale x 16 x i8> %res
}

define <vscale x 8 x i16> @test_svqshrn_n_u16_u32_x2(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) {
; CHECK-LABEL: test_svqshrn_n_u16_u32_x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uqshrn z0.h, { z0.s, z1.s }, #16
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshrn.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm, i32 16)
  ret <vscale x 8 x i16> %res
}

define <vscale x 8 x i16> @test_svqshrun_n_u16_s32_x2(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) {
; CHECK-LABEL: test_svqshrun_n_u16_s32_x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sqshrun z0.h, { z0.s, z1.s }, #16
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrun.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm, i32 16)
  ret <vscale x 8 x i16> %res
}

define <vscale x 16 x i8> @test_svqshrun_n_u8_s16_x2(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
; CHECK-LABEL: test_svqshrun_n_u8_s16_x2:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sqshrun z0.b, { z0.h, z1.h }, #8
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrun.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 8)
  ret <vscale x 16 x i8> %res
}