; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 -global-isel=true -new-reg-bank-select %s -o - | FileCheck %s

define void @test(ptr %p) {
; CHECK-LABEL: test:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    v_mov_b32_e32 v2, v1
; CHECK-NEXT:    ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
; CHECK-NEXT:    v_mov_b32_e32 v1, v2
; CHECK-NEXT:    s_mov_b32 s8, 16
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    v_mov_b32_e32 v2, s6
; CHECK-NEXT:    v_cvt_f32_ubyte0_e64 v2, v2
; CHECK-NEXT:    v_rcp_iflag_f32_e64 v2, v2
; CHECK-NEXT:    s_mov_b32 s5, 0x4f7ffffe
; CHECK-NEXT:    v_mov_b32_e32 v3, s5
; CHECK-NEXT:    v_mul_f32_e64 v2, v2, v3
; CHECK-NEXT:    v_cvt_u32_f32_e64 v2, v2
; CHECK-NEXT:    v_readfirstlane_b32 s4, v2
; CHECK-NEXT:    s_mov_b32 s7, 0
; CHECK-NEXT:    s_mul_hi_u32 s7, s4, s7
; CHECK-NEXT:    s_add_i32 s4, s4, s7
; CHECK-NEXT:    s_mul_hi_u32 s4, s4, s8
; CHECK-NEXT:    s_mov_b32 s7, 2
; CHECK-NEXT:    s_add_i32 s4, s4, s7
; CHECK-NEXT:    v_mov_b32_e32 v2, s6
; CHECK-NEXT:    v_cvt_f32_ubyte0_e64 v2, v2
; CHECK-NEXT:    v_rcp_iflag_f32_e64 v2, v2
; CHECK-NEXT:    v_mov_b32_e32 v3, s5
; CHECK-NEXT:    v_mul_f32_e64 v2, v2, v3
; CHECK-NEXT:    v_cvt_u32_f32_e64 v2, v2
; CHECK-NEXT:    v_readfirstlane_b32 s7, v2
; CHECK-NEXT:    s_mov_b32 s9, 0
; CHECK-NEXT:    s_mul_hi_u32 s9, s7, s9
; CHECK-NEXT:    s_add_i32 s7, s7, s9
; CHECK-NEXT:    s_mul_hi_u32 s7, s7, s8
; CHECK-NEXT:    s_mov_b32 s9, 2
; CHECK-NEXT:    s_add_i32 s9, s7, s9
; CHECK-NEXT:    v_mov_b32_e32 v2, s6
; CHECK-NEXT:    v_cvt_f32_ubyte0_e64 v2, v2
; CHECK-NEXT:    v_rcp_iflag_f32_e64 v2, v2
; CHECK-NEXT:    v_mov_b32_e32 v3, s5
; CHECK-NEXT:    v_mul_f32_e64 v2, v2, v3
; CHECK-NEXT:    v_cvt_u32_f32_e64 v2, v2
; CHECK-NEXT:    v_readfirstlane_b32 s7, v2
; CHECK-NEXT:    s_mov_b32 s10, 0
; CHECK-NEXT:    s_mul_hi_u32 s10, s7, s10
; CHECK-NEXT:    s_add_i32 s7, s7, s10
; CHECK-NEXT:    s_mul_hi_u32 s7, s7, s8
; CHECK-NEXT:    s_mov_b32 s10, 2
; CHECK-NEXT:    s_add_i32 s7, s7, s10
; CHECK-NEXT:    v_mov_b32_e32 v2, s6
; CHECK-NEXT:    v_cvt_f32_ubyte0_e64 v2, v2
; CHECK-NEXT:    v_rcp_iflag_f32_e64 v2, v2
; CHECK-NEXT:    v_mov_b32_e32 v3, s5
; CHECK-NEXT:    v_mul_f32_e64 v2, v2, v3
; CHECK-NEXT:    v_cvt_u32_f32_e64 v2, v2
; CHECK-NEXT:    v_readfirstlane_b32 s5, v2
; CHECK-NEXT:    s_mov_b32 s6, 0
; CHECK-NEXT:    s_mul_hi_u32 s6, s5, s6
; CHECK-NEXT:    s_add_i32 s5, s5, s6
; CHECK-NEXT:    s_mul_hi_u32 s5, s5, s8
; CHECK-NEXT:    s_mov_b32 s6, 2
; CHECK-NEXT:    s_add_i32 s5, s5, s6
; CHECK-NEXT:    s_mov_b32 s6, 0xff
; CHECK-NEXT:    s_and_b32 s4, s4, s6
; CHECK-NEXT:    s_and_b32 s9, s9, s6
; CHECK-NEXT:    s_mov_b32 s10, 8
; CHECK-NEXT:    s_lshl_b32 s9, s9, s10
; CHECK-NEXT:    s_or_b32 s4, s4, s9
; CHECK-NEXT:    s_and_b32 s7, s7, s6
; CHECK-NEXT:    s_lshl_b32 s7, s7, s8
; CHECK-NEXT:    s_or_b32 s4, s4, s7
; CHECK-NEXT:    s_and_b32 s5, s5, s6
; CHECK-NEXT:    s_mov_b32 s6, 24
; CHECK-NEXT:    s_lshl_b32 s5, s5, s6
; CHECK-NEXT:    s_or_b32 s4, s4, s5
; CHECK-NEXT:    v_mov_b32_e32 v2, s4
; CHECK-NEXT:    flat_store_dword v[0:1], v2
; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_setpc_b64 s[30:31]
  %B = udiv <4 x i8> splat (i8 16), zeroinitializer
  store <4 x i8> %B, ptr %p, align 4
  ret void
}