; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100 -O3 | FileCheck %s --check-prefix=PIPELINE
; RUN: opt < %s -passes='gvn<no-scalar-pre>' -S | llc -mtriple=nvptx64 -mcpu=sm_100 -O0 | FileCheck %s --check-prefix=NO-SCALAR-PRE
; RUN: opt < %s -passes='gvn<scalar-pre>' -S | llc -mtriple=nvptx64 -mcpu=sm_100 -O0 | FileCheck %s --check-prefix=SCALAR-PRE

; Scalar PRE inserts a critical-edge computation and a PHI for the common add.
; That shape needs more NVPTX virtual registers than keeping the duplicated adds.

define void @test_scalar_pre_option(ptr %arr, i8 %cond) {
; PIPELINE-LABEL: test_scalar_pre_option(
; PIPELINE:       {
; PIPELINE-NEXT:    .reg .pred %p<2>;
; PIPELINE-NEXT:    .reg .b16 %rs<2>;
; PIPELINE-NEXT:    .reg .b32 %r<3>;
; PIPELINE-NEXT:    .reg .b64 %rd<2>;
; PIPELINE-EMPTY:
; PIPELINE-NEXT:  // %bb.0: // %entry
; PIPELINE-NEXT:    ld.param.b64 %rd1, [test_scalar_pre_option_param_0];
; PIPELINE-NEXT:    ld.param.b8 %rs1, [test_scalar_pre_option_param_1];
; PIPELINE-NEXT:    setp.eq.b16 %p1, %rs1, 0;
; PIPELINE-NEXT:    ld.b32 %r2, [%rd1];
; PIPELINE-NEXT:    add.s32 %r1, %r2, 2;
; PIPELINE-NEXT:    @%p1 bra $L__BB0_2;
; PIPELINE-NEXT:  // %bb.1: // %if.then
; PIPELINE-NEXT:    st.b32 [%rd1+8], %r1;
; PIPELINE-NEXT:  $L__BB0_2: // %if.end
; PIPELINE-NEXT:    st.b32 [%rd1+12], %r1;
; PIPELINE-NEXT:    ret;
;
; NO-SCALAR-PRE-LABEL: test_scalar_pre_option(
; NO-SCALAR-PRE:       {
; NO-SCALAR-PRE-NEXT:    .reg .pred %p<2>;
; NO-SCALAR-PRE-NEXT:    .reg .b16 %rs<2>;
; NO-SCALAR-PRE-NEXT:    .reg .b32 %r<4>;
; NO-SCALAR-PRE-NEXT:    .reg .b64 %rd<2>;
; NO-SCALAR-PRE-EMPTY:
; NO-SCALAR-PRE-NEXT:  // %bb.0: // %entry
; NO-SCALAR-PRE-NEXT:    ld.param.b8 %rs1, [test_scalar_pre_option_param_1];
; NO-SCALAR-PRE-NEXT:    ld.param.b64 %rd1, [test_scalar_pre_option_param_0];
; NO-SCALAR-PRE-NEXT:    setp.eq.b16 %p1, %rs1, 0;
; NO-SCALAR-PRE-NEXT:    ld.b32 %r1, [%rd1];
; NO-SCALAR-PRE-NEXT:    @%p1 bra $L__BB0_2;
; NO-SCALAR-PRE-NEXT:    bra.uni $L__BB0_1;
; NO-SCALAR-PRE-NEXT:  $L__BB0_1: // %if.then
; NO-SCALAR-PRE-NEXT:    add.s32 %r2, %r1, 2;
; NO-SCALAR-PRE-NEXT:    st.b32 [%rd1+8], %r2;
; NO-SCALAR-PRE-NEXT:    bra.uni $L__BB0_2;
; NO-SCALAR-PRE-NEXT:  $L__BB0_2: // %if.end
; NO-SCALAR-PRE-NEXT:    add.s32 %r3, %r1, 2;
; NO-SCALAR-PRE-NEXT:    st.b32 [%rd1+12], %r3;
; NO-SCALAR-PRE-NEXT:    ret;
;
; SCALAR-PRE-LABEL: test_scalar_pre_option(
; SCALAR-PRE:       {
; SCALAR-PRE-NEXT:    .reg .pred %p<2>;
; SCALAR-PRE-NEXT:    .reg .b16 %rs<2>;
; SCALAR-PRE-NEXT:    .reg .b32 %r<6>;
; SCALAR-PRE-NEXT:    .reg .b64 %rd<2>;
; SCALAR-PRE-EMPTY:
; SCALAR-PRE-NEXT:  // %bb.0: // %entry
; SCALAR-PRE-NEXT:    ld.param.b8 %rs1, [test_scalar_pre_option_param_1];
; SCALAR-PRE-NEXT:    ld.param.b64 %rd1, [test_scalar_pre_option_param_0];
; SCALAR-PRE-NEXT:    setp.ne.b16 %p1, %rs1, 0;
; SCALAR-PRE-NEXT:    ld.b32 %r1, [%rd1];
; SCALAR-PRE-NEXT:    @%p1 bra $L__BB0_2;
; SCALAR-PRE-NEXT:    bra.uni $L__BB0_1;
; SCALAR-PRE-NEXT:  $L__BB0_1: // %entry.if.end_crit_edge
; SCALAR-PRE-NEXT:    add.s32 %r2, %r1, 2;
; SCALAR-PRE-NEXT:    mov.b32 %r5, %r2;
; SCALAR-PRE-NEXT:    bra.uni $L__BB0_3;
; SCALAR-PRE-NEXT:  $L__BB0_2: // %if.then
; SCALAR-PRE-NEXT:    add.s32 %r3, %r1, 2;
; SCALAR-PRE-NEXT:    st.b32 [%rd1+8], %r3;
; SCALAR-PRE-NEXT:    mov.b32 %r5, %r3;
; SCALAR-PRE-NEXT:    bra.uni $L__BB0_3;
; SCALAR-PRE-NEXT:  $L__BB0_3: // %if.end
; SCALAR-PRE-NEXT:    mov.b32 %r4, %r5;
; SCALAR-PRE-NEXT:    st.b32 [%rd1+12], %r4;
; SCALAR-PRE-NEXT:    ret;
entry:
  %tobool.not = icmp eq i8 %cond, 0
  %tmp7.pre = load i32, ptr %arr, align 4
  br i1 %tobool.not, label %if.end, label %if.then

if.then:
  %add = add nsw i32 %tmp7.pre, 2
  %getElem = getelementptr inbounds nuw i8, ptr %arr, i64 8
  store i32 %add, ptr %getElem, align 4
  br label %if.end

if.end:
  %add8 = add nsw i32 %tmp7.pre, 2
  %getElem1 = getelementptr inbounds nuw i8, ptr %arr, i64 12
  store i32 %add8, ptr %getElem1, align 4
  ret void
}