// COM: A0 tensor multicast-mask clearing when several tensor_load_to_lds share // COM: one descriptor base built once. The single mask-set is cleared and every // COM: tensor that reads the base is covered; the clear is applied once. // RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf // RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \ // RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \ // RUN: --output %t.out.elf \ // RUN: 2>&1 \ // RUN: | %FileCheck --check-prefix=API %s // API: hotswap: tensor_load_to_lds: cleared workgroup_mask at descriptor definition 0x{{[0-9A-F]+}} (s4) // API-NOT: hotswap: tensor_load_to_lds: cleared workgroup_mask at descriptor definition // API: hotswap: applied 1 instruction patches // API: RESULT: SUCCESS // RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=DISASM %s // DISASM-LABEL: : // DISASM: s_and_b32 s4, s4, 0xfff70000 // DISASM: tensor_load_to_lds s[0:3], s[4:11] // DISASM: tensor_load_to_lds s[0:3], s[4:11] // RUN: hotswap-rewrite %t.out.elf \ // RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \ // RUN: --check-idempotent \ // RUN: | %FileCheck --check-prefix=IDEM %s // IDEM: IDEMPOTENT: YES .amdgcn_target "amdgcn-amd-amdhsa--gfx1250" .text .globl test_tensor_mask_multi .p2align 8 .type test_tensor_mask_multi,@function test_tensor_mask_multi: s_mov_b32 s4, 0 s_and_b32 s4, s4, 0xfffcffff s_or_b32 s4, s4, s5 s_and_b32 s4, s4, 0xfff7ffff tensor_load_to_lds s[0:3], s[4:11] tensor_load_to_lds s[0:3], s[4:11] s_endpgm s_nop 0 s_nop 0 s_nop 0 s_nop 0 s_nop 0 s_nop 0 s_nop 0 s_nop 0 .Ltest_tensor_mask_multi_end: .size test_tensor_mask_multi, .Ltest_tensor_mask_multi_end-test_tensor_mask_multi .rodata .p2align 8 .amdhsa_kernel test_tensor_mask_multi .amdhsa_next_free_vgpr 1 .amdhsa_next_free_sgpr 12 .end_amdhsa_kernel .amdgpu_metadata amdhsa.version: - 3 - 0 amdhsa.kernels: - .name: test_tensor_mask_multi .symbol: test_tensor_mask_multi.kd .sgpr_count: 12 .vgpr_count: 1 .kernarg_segment_size: 0 .group_segment_fixed_size: 0 .private_segment_fixed_size: 0 .kernarg_segment_align: 8 .wavefront_size: 64 .max_flat_workgroup_size: 256 .end_amdgpu_metadata