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81 lines
4.8 KiB
Plaintext
81 lines
4.8 KiB
Plaintext
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -O1 -triple amdgcn-amd-amdhsa -target-cpu verde -emit-llvm -fcuda-is-device -o - %s | FileCheck %s
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#define __device__ __attribute__((device))
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typedef float v4f32 __attribute__((ext_vector_type(4)));
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typedef _Float16 v4f16 __attribute__((ext_vector_type(4)));
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// CHECK-LABEL: @_Z33test_raw_buffer_load_format_v4f32u22__amdgpu_buffer_rsrc_tii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call contract <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.format.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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__device__ v4f32 test_raw_buffer_load_format_v4f32(__amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
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return __builtin_amdgcn_raw_buffer_load_format_v4f32(rsrc, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z33test_raw_buffer_load_format_v4f16u22__amdgpu_buffer_rsrc_tii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call contract <4 x half> @llvm.amdgcn.raw.ptr.buffer.load.format.v4f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret <4 x half> [[TMP0]]
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//
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__device__ v4f16 test_raw_buffer_load_format_v4f16(__amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
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return __builtin_amdgcn_raw_buffer_load_format_v4f16(rsrc, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z34test_raw_buffer_store_format_v4f32Dv4_fu22__amdgpu_buffer_rsrc_tii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.amdgcn.raw.ptr.buffer.store.format.v4f32(<4 x float> [[VDATA:%.*]], ptr addrspace(8) [[RSRC:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret void
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//
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__device__ void test_raw_buffer_store_format_v4f32(v4f32 vdata, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
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__builtin_amdgcn_raw_buffer_store_format_v4f32(vdata, rsrc, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z34test_raw_buffer_store_format_v4f16Dv4_DF16_u22__amdgpu_buffer_rsrc_tii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.amdgcn.raw.ptr.buffer.store.format.v4f16(<4 x half> [[VDATA:%.*]], ptr addrspace(8) [[RSRC:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret void
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//
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__device__ void test_raw_buffer_store_format_v4f16(v4f16 vdata, __amdgpu_buffer_rsrc_t rsrc, int offset, int soffset) {
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__builtin_amdgcn_raw_buffer_store_format_v4f16(vdata, rsrc, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z36test_struct_buffer_load_format_v4f32u22__amdgpu_buffer_rsrc_tiii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call contract <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) [[RSRC:%.*]], i32 [[VINDEX:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret <4 x float> [[TMP0]]
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//
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__device__ v4f32 test_struct_buffer_load_format_v4f32(__amdgpu_buffer_rsrc_t rsrc, int vindex, int offset, int soffset) {
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return __builtin_amdgcn_struct_buffer_load_format_v4f32(rsrc, vindex, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z36test_struct_buffer_load_format_v4f16u22__amdgpu_buffer_rsrc_tiii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call contract <4 x half> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f16(ptr addrspace(8) [[RSRC:%.*]], i32 [[VINDEX:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret <4 x half> [[TMP0]]
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//
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__device__ v4f16 test_struct_buffer_load_format_v4f16(__amdgpu_buffer_rsrc_t rsrc, int vindex, int offset, int soffset) {
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return __builtin_amdgcn_struct_buffer_load_format_v4f16(rsrc, vindex, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z37test_struct_buffer_store_format_v4f32Dv4_fu22__amdgpu_buffer_rsrc_tiii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f32(<4 x float> [[VDATA:%.*]], ptr addrspace(8) [[RSRC:%.*]], i32 [[VINDEX:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret void
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//
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__device__ void test_struct_buffer_store_format_v4f32(v4f32 vdata, __amdgpu_buffer_rsrc_t rsrc, int vindex, int offset, int soffset) {
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__builtin_amdgcn_struct_buffer_store_format_v4f32(vdata, rsrc, vindex, offset, soffset, 0);
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}
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// CHECK-LABEL: @_Z37test_struct_buffer_store_format_v4f16Dv4_DF16_u22__amdgpu_buffer_rsrc_tiii(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: tail call void @llvm.amdgcn.struct.ptr.buffer.store.format.v4f16(<4 x half> [[VDATA:%.*]], ptr addrspace(8) [[RSRC:%.*]], i32 [[VINDEX:%.*]], i32 [[OFFSET:%.*]], i32 [[SOFFSET:%.*]], i32 0)
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// CHECK-NEXT: ret void
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//
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__device__ void test_struct_buffer_store_format_v4f16(v4f16 vdata, __amdgpu_buffer_rsrc_t rsrc, int vindex, int offset, int soffset) {
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__builtin_amdgcn_struct_buffer_store_format_v4f16(vdata, rsrc, vindex, offset, soffset, 0);
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}
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