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215 lines
11 KiB
TableGen
215 lines
11 KiB
TableGen
//===-- RISCVInstrInfoZa.td - RISC-V Atomic instructions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard atomic 'Za*'
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// extensions:
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// - Zawrs (v1.0) : Wait-on-Reservation-Set.
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// - Zacas (v1.0) : Atomic Compare-and-Swap.
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// - Zabha (v1.0) : Byte and Halfword Atomic Memory Operations.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Zacas (Atomic Compare-and-Swap)
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//===----------------------------------------------------------------------===//
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def GPRPairRV32Operand : AsmOperandClass {
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let Name = "GPRPairRV32";
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let ParserMethod = "parseGPRPair<false>";
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let PredicateMethod = "isGPRPair";
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let RenderMethod = "addRegOperands";
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}
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def GPRPairRV64Operand : AsmOperandClass {
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let Name = "GPRPairRV64";
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let ParserMethod = "parseGPRPair<true>";
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let PredicateMethod = "isGPRPair";
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let RenderMethod = "addRegOperands";
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}
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def GPRPairRV32 : RegisterOperand<GPRPair> {
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let ParserMatchClass = GPRPairRV32Operand;
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}
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def GPRPairRV64 : RegisterOperand<GPRPair> {
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let ParserMatchClass = GPRPairRV64Operand;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "$rd = $rd_wb" in
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class AMO_cas<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr,
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DAGOperand RC>
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: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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(outs RC:$rd_wb), (ins RC:$rd, RC:$rs2, GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs2, $rs1">;
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multiclass AMO_cas_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
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DAGOperand RC> {
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def "" : AMO_cas<funct5, 0, 0, funct3, opcodestr, RC>;
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def _AQ : AMO_cas<funct5, 1, 0, funct3, opcodestr # ".aq", RC>;
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def _RL : AMO_cas<funct5, 0, 1, funct3, opcodestr # ".rl", RC>;
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def _AQRL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>;
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}
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let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
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defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
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} // Predicates = [HasStdExtZacas]
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let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Only" in {
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defm AMOCAS_D_RV32 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPRPairRV32>;
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} // Predicates = [HasStdExtZacas, IsRV32]
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let Predicates = [HasStdExtZacas, IsRV64] in {
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defm AMOCAS_D_RV64 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPR>;
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defm AMOCAS_Q : AMO_cas_aq_rl<0b00101, 0b100, "amocas.q", GPRPairRV64>;
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} // Predicates = [HasStdExtZacas, IsRV64]
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multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
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list<Predicate> ExtraPreds = []> {
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let Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds) in {
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def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst#"_AQ") GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst#"_RL") GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$new, GPR:$addr)>;
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} // Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds)
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let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in {
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def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_release") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
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def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (XLenVT GPR:$addr),
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(vt GPR:$cmp),
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(vt GPR:$new)),
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(!cast<RVInst>(BaseInst) GPR:$cmp, GPR:$new, GPR:$addr)>;
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} // Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds)
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}
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defm : AMOCASPat<"atomic_cmp_swap_i32", "AMOCAS_W">;
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defm : AMOCASPat<"atomic_cmp_swap_i64", "AMOCAS_D_RV64", i64, [IsRV64]>;
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//===----------------------------------------------------------------------===//
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// Zawrs (Wait-on-Reservation-Set)
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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class WRSInst<bits<12> funct12, string opcodestr>
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: RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> {
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let rs1 = 0;
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let rd = 0;
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let imm12 = funct12;
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}
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let Predicates = [HasStdExtZawrs] in {
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def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>;
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def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>;
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} // Predicates = [HasStdExtZawrs]
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//===----------------------------------------------------------------------===//
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// Zabha (Byte and Halfword Atomic Memory Operations)
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZabha], IsSignExtendingOpW = 1 in {
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defm AMOSWAP_B : AMO_rr_aq_rl<0b00001, 0b000, "amoswap.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOADD_B : AMO_rr_aq_rl<0b00000, 0b000, "amoadd.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOXOR_B : AMO_rr_aq_rl<0b00100, 0b000, "amoxor.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOAND_B : AMO_rr_aq_rl<0b01100, 0b000, "amoand.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOOR_B : AMO_rr_aq_rl<0b01000, 0b000, "amoor.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOMIN_B : AMO_rr_aq_rl<0b10000, 0b000, "amomin.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOMAX_B : AMO_rr_aq_rl<0b10100, 0b000, "amomax.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOMINU_B : AMO_rr_aq_rl<0b11000, 0b000, "amominu.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOMAXU_B : AMO_rr_aq_rl<0b11100, 0b000, "amomaxu.b">,
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Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>;
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defm AMOSWAP_H : AMO_rr_aq_rl<0b00001, 0b001, "amoswap.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOADD_H : AMO_rr_aq_rl<0b00000, 0b001, "amoadd.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOXOR_H : AMO_rr_aq_rl<0b00100, 0b001, "amoxor.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOAND_H : AMO_rr_aq_rl<0b01100, 0b001, "amoand.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOOR_H : AMO_rr_aq_rl<0b01000, 0b001, "amoor.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOMIN_H : AMO_rr_aq_rl<0b10000, 0b001, "amomin.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOMAX_H : AMO_rr_aq_rl<0b10100, 0b001, "amomax.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOMINU_H : AMO_rr_aq_rl<0b11000, 0b001, "amominu.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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defm AMOMAXU_H : AMO_rr_aq_rl<0b11100, 0b001, "amomaxu.h">,
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Sched<[WriteAtomicH, ReadAtomicHA, ReadAtomicHD]>;
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}
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// If Zacas extension is also implemented, Zabha further provides AMOCAS.[B|H].
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let Predicates = [HasStdExtZabha, HasStdExtZacas], IsSignExtendingOpW = 1 in {
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defm AMOCAS_B : AMO_cas_aq_rl<0b00101, 0b000, "amocas.b", GPR>;
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defm AMOCAS_H : AMO_cas_aq_rl<0b00101, 0b001, "amocas.h", GPR>;
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}
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/// AMOs
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defm : AMOPat<"atomic_swap_i8", "AMOSWAP_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_add_i8", "AMOADD_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_and_i8", "AMOAND_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_or_i8", "AMOOR_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_xor_i8", "AMOXOR_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_max_i8", "AMOMAX_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_min_i8", "AMOMIN_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_umax_i8", "AMOMAXU_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_umin_i8", "AMOMINU_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_swap_i16", "AMOSWAP_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_add_i16", "AMOADD_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_and_i16", "AMOAND_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_or_i16", "AMOOR_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_xor_i16", "AMOXOR_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_max_i16", "AMOMAX_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_min_i16", "AMOMIN_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_umax_i16", "AMOMAXU_H", XLenVT, [HasStdExtZabha]>;
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defm : AMOPat<"atomic_load_umin_i16", "AMOMINU_H", XLenVT, [HasStdExtZabha]>;
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/// AMOCAS
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defm : AMOCASPat<"atomic_cmp_swap_i8", "AMOCAS_B", XLenVT, [HasStdExtZabha]>;
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defm : AMOCASPat<"atomic_cmp_swap_i16", "AMOCAS_H", XLenVT, [HasStdExtZabha]>;
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