derek.holloway
7502bf64a4
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585 lines
24 KiB
TableGen
585 lines
24 KiB
TableGen
//===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'Zvfbfmin'
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// extension, providing vector conversion instructions for BFloat16.
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// This version is still experimental as the 'Zvfbfmin' extension hasn't been
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// ratified yet.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let ElementsDependOn = EltDepsNone in {
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let Predicates = [HasStdExtZvfbfminOrZvfofp8min],
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Constraints = "@earlyclobber $vd",
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mayRaiseFPException = true in {
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let VS1VS2Constraint = WidenCvt, DestEEW = EEWSEWx2 in
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def VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>;
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let Uses = [FRM, VL, VTYPE] in
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def VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>;
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}
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let Predicates = [HasStdExtZvfbfwma],
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Uses = [FRM, VL, VTYPE], mayRaiseFPException = true,
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DestEEW = EEWSEWx2 in {
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defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>;
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}
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} // ElementsDependOn = EltDepsNone
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZvfbfmin] in {
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defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V;
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defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
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}
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let mayRaiseFPException = true, Predicates = [HasStdExtZvfbfwma] in
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defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
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defset list<VTypeInfoToWide> AllWidenableIntToBF16Vectors = {
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def : VTypeInfoToWide<VI8MF8, VBF16MF4>;
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def : VTypeInfoToWide<VI8MF4, VBF16MF2>;
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def : VTypeInfoToWide<VI8MF2, VBF16M1>;
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def : VTypeInfoToWide<VI8M1, VBF16M2>;
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def : VTypeInfoToWide<VI8M2, VBF16M4>;
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def : VTypeInfoToWide<VI8M4, VBF16M8>;
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}
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multiclass VPseudoVALU_VV_VF_RM_BF16 {
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foreach m = MxListF in {
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defm "" : VPseudoBinaryFV_VV_RM<m, 16/*sew*/>,
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SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX,
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16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxList in {
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defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
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SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVALU_VF_RM_BF16 {
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defvar f = SCALAR_F16;
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foreach m = f.MxList in {
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defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
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SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVFWALU_VV_VF_RM_BF16 {
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foreach m = MxListFW in {
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defm "" : VPseudoBinaryW_VV_RM<m, sew=16>,
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SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
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16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxListFW in {
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defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,
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SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVFWALU_WV_WF_RM_BF16 {
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foreach m = MxListFW in {
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defm "" : VPseudoBinaryW_WV_RM<m, sew=16>,
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SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
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16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxListFW in {
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defm "" : VPseudoBinaryW_WF_RM<m, f, sew=f.SEW>,
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SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVFMUL_VV_VF_RM_BF16 {
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foreach m = MxListF in {
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defm "" : VPseudoBinaryFV_VV_RM<m, 16/*sew*/>,
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SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX,
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16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxList in {
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defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
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SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVWMUL_VV_VF_RM_BF16 {
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foreach m = MxListFW in {
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defm "" : VPseudoBinaryW_VV_RM<m, sew=16>,
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SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX,
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16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxListFW in {
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defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,
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SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVMAC_VV_VF_AAXA_RM_BF16 {
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foreach m = MxListF in {
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defm "" : VPseudoTernaryV_VV_AAXA_RM<m, 16/*sew*/>,
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SchedTernary<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV",
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"ReadVFMulAddV", m.MX, 16/*sew*/>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxList in {
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defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, f.SEW>,
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SchedTernary<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF",
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"ReadVFMulAddV", m.MX, f.SEW>;
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}
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}
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multiclass VPseudoVWMAC_VV_VF_RM_BF16 {
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foreach m = MxListFW in {
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defm "" : VPseudoTernaryW_VV_RM<m, sew=16>,
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SchedTernary<"WriteVFWMulAddV", "ReadVFWMulAddV",
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"ReadVFWMulAddV", "ReadVFWMulAddV", m.MX, 16/*sew*/>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxListFW in {
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defm "" : VPseudoTernaryW_VF_RM<m, f, sew=f.SEW>,
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SchedTernary<"WriteVFWMulAddF", "ReadVFWMulAddV",
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"ReadVFWMulAddF", "ReadVFWMulAddV", m.MX, f.SEW>;
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}
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}
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multiclass VPseudoVRCP_V_BF16 {
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foreach m = MxListF in {
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defvar mx = m.MX;
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let VLMul = m.value in {
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def "_V_" # mx # "_E16"
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: VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
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SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,
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forcePassthruRead=true>;
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def "_V_" # mx # "_E16_MASK"
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: VPseudoUnaryMask<m.vrclass, m.vrclass>,
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RISCVMaskedPseudo<MaskIdx = 2>,
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SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,
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forcePassthruRead=true>;
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}
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}
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}
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multiclass VPseudoVRCP_V_RM_BF16 {
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foreach m = MxListF in {
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defvar mx = m.MX;
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let VLMul = m.value in {
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def "_V_" # mx # "_E16"
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: VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
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SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,
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forcePassthruRead=true>;
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def "_V_" # mx # "_E16_MASK"
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: VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
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RISCVMaskedPseudo<MaskIdx = 2>,
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SchedUnary<"WriteVFRecpV", "ReadVFRecpV", mx, 16/*sew*/,
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forcePassthruRead=true>;
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}
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}
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}
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multiclass VPseudoVMAX_VV_VF_BF16 {
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foreach m = MxListF in {
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defm "" : VPseudoBinaryV_VV<m, sew=16>,
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SchedBinary<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV",
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m.MX, 16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxList in {
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defm "" : VPseudoBinaryV_VF<m, f, f.SEW>,
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SchedBinary<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF",
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m.MX, f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVSGNJ_VV_VF_BF16 {
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foreach m = MxListF in {
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defm "" : VPseudoBinaryV_VV<m, sew=16>,
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SchedBinary<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV", m.MX,
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16/*sew*/, forcePassthruRead=true>;
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}
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defvar f = SCALAR_F16;
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foreach m = f.MxList in {
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defm "" : VPseudoBinaryV_VF<m, f, f.SEW>,
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SchedBinary<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF", m.MX,
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f.SEW, forcePassthruRead=true>;
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}
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}
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multiclass VPseudoVWCVTF_V_BF16 {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxListW in
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defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=8,
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TargetConstraintType=3>,
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SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX, 8/*sew*/,
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forcePassthruRead=true>;
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}
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multiclass VPseudoVWCVTD_V_BF16 {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxListFW in
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defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=16,
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TargetConstraintType=3>,
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SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX, 16/*sew*/,
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forcePassthruRead=true>;
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}
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multiclass VPseudoVNCVTD_W_BF16 {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxListFW in
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defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, sew=16,
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TargetConstraintType=2>,
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SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16/*sew*/,
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forcePassthruRead=true>;
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}
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multiclass VPseudoVNCVTD_W_RM_BF16 {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxListFW in
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defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
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constraint, sew=16,
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TargetConstraintType=2>,
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SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16/*sew*/,
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forcePassthruRead=true>;
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}
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let Predicates = [HasVInstructionsBF16], AltFmtType = IS_ALTFMT in {
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let mayRaiseFPException = true in {
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defm PseudoVFADD_ALT : VPseudoVALU_VV_VF_RM_BF16;
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defm PseudoVFSUB_ALT : VPseudoVALU_VV_VF_RM_BF16;
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defm PseudoVFRSUB_ALT : VPseudoVALU_VF_RM_BF16;
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}
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let mayRaiseFPException = true in {
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defm PseudoVFWADD_ALT : VPseudoVFWALU_VV_VF_RM_BF16;
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defm PseudoVFWSUB_ALT : VPseudoVFWALU_VV_VF_RM_BF16;
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defm PseudoVFWADD_ALT : VPseudoVFWALU_WV_WF_RM_BF16;
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defm PseudoVFWSUB_ALT : VPseudoVFWALU_WV_WF_RM_BF16;
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}
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let mayRaiseFPException = true in
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defm PseudoVFMUL_ALT : VPseudoVFMUL_VV_VF_RM_BF16;
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let mayRaiseFPException = true in
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defm PseudoVFWMUL_ALT : VPseudoVWMUL_VV_VF_RM_BF16;
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let mayRaiseFPException = true in {
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defm PseudoVFMACC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFNMACC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFMSAC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFNMSAC_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFMADD_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFNMADD_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFMSUB_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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defm PseudoVFNMSUB_ALT : VPseudoVMAC_VV_VF_AAXA_RM_BF16;
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}
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let mayRaiseFPException = true in {
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defm PseudoVFWMACC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;
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defm PseudoVFWNMACC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;
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defm PseudoVFWMSAC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;
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defm PseudoVFWNMSAC_ALT : VPseudoVWMAC_VV_VF_RM_BF16;
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}
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let mayRaiseFPException = true in
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defm PseudoVFRSQRT7_ALT : VPseudoVRCP_V_BF16;
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let mayRaiseFPException = true in
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defm PseudoVFREC7_ALT : VPseudoVRCP_V_RM_BF16;
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let mayRaiseFPException = true in {
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defm PseudoVFMIN_ALT : VPseudoVMAX_VV_VF_BF16;
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defm PseudoVFMAX_ALT : VPseudoVMAX_VV_VF_BF16;
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}
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defm PseudoVFSGNJ_ALT : VPseudoVSGNJ_VV_VF_BF16;
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defm PseudoVFSGNJN_ALT : VPseudoVSGNJ_VV_VF_BF16;
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defm PseudoVFSGNJX_ALT : VPseudoVSGNJ_VV_VF_BF16;
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let mayRaiseFPException = true in {
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defm PseudoVMFEQ_ALT : VPseudoVCMPM_VV_VF;
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defm PseudoVMFNE_ALT : VPseudoVCMPM_VV_VF;
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defm PseudoVMFLT_ALT : VPseudoVCMPM_VV_VF;
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defm PseudoVMFLE_ALT : VPseudoVCMPM_VV_VF;
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defm PseudoVMFGT_ALT : VPseudoVCMPM_VF;
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defm PseudoVMFGE_ALT : VPseudoVCMPM_VF;
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}
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defm PseudoVFCLASS_ALT : VPseudoVCLS_V;
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defm PseudoVFMERGE_ALT : VPseudoVMRG_FM;
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defm PseudoVFMV_V_ALT : VPseudoVMV_F;
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let mayRaiseFPException = true in {
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defm PseudoVFWCVT_F_XU_ALT : VPseudoVWCVTF_V_BF16;
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defm PseudoVFWCVT_F_X_ALT : VPseudoVWCVTF_V_BF16;
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defm PseudoVFWCVT_F_F_ALT : VPseudoVWCVTD_V_BF16;
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} // mayRaiseFPException = true
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let mayRaiseFPException = true in {
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let hasSideEffects = 0, hasPostISelHook = 1 in {
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defm PseudoVFNCVT_XU_F_ALT : VPseudoVNCVTI_W_RM;
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defm PseudoVFNCVT_X_F_ALT : VPseudoVNCVTI_W_RM;
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}
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defm PseudoVFNCVT_RTZ_XU_F_ALT : VPseudoVNCVTI_W;
|
|
defm PseudoVFNCVT_RTZ_X_F_ALT : VPseudoVNCVTI_W;
|
|
|
|
defm PseudoVFNCVT_F_F_ALT : VPseudoVNCVTD_W_RM_BF16;
|
|
|
|
defm PseudoVFNCVT_ROD_F_F_ALT : VPseudoVNCVTD_W_BF16;
|
|
} // mayRaiseFPException = true
|
|
|
|
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
|
|
defvar f = SCALAR_F16;
|
|
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
|
|
def "PseudoVFMV_" # f.FX # "_S_ALT" :
|
|
RISCVVPseudo<(outs f.fprclass:$rd), (ins VR:$rs2, sew:$sew)>,
|
|
Sched<[WriteVMovFS, ReadVMovFS]>;
|
|
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,
|
|
Constraints = "$rd = $passthru" in
|
|
def "PseudoVFMV_S_" # f.FX # "_ALT" :
|
|
RISCVVPseudo<(outs VR:$rd),
|
|
(ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew)>,
|
|
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
|
|
}
|
|
|
|
defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF<"@earlyclobber $rd">;
|
|
defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF;
|
|
} // Predicates = [HasVInstructionsBF16], AltFmtType = IS_ALTFMT
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
multiclass VPatConversionWF_VF_BF<string intrinsic, string instruction,
|
|
bit isSEWAware = 0> {
|
|
foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in
|
|
{
|
|
defvar fvti = fvtiToFWti.Vti;
|
|
defvar fwti = fvtiToFWti.Wti;
|
|
defm : VPatConversion<intrinsic, instruction, "V",
|
|
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
|
|
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatConversionVF_WF_BF_RM<string intrinsic, string instruction,
|
|
bit isSEWAware = 0> {
|
|
foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {
|
|
defvar fvti = fvtiToFWti.Vti;
|
|
defvar fwti = fvtiToFWti.Wti;
|
|
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
|
|
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
|
|
fvti.LMul, fvti.RegClass, fwti.RegClass,
|
|
isSEWAware>;
|
|
}
|
|
}
|
|
|
|
let Predicates = [HasStdExtZvfbfmin] in {
|
|
defm : VPatConversionWF_VF_BF<"int_riscv_vfwcvtbf16_f_f_v",
|
|
"PseudoVFWCVTBF16_F_F", isSEWAware=1>;
|
|
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
|
|
"PseudoVFNCVTBF16_F_F", isSEWAware=1>;
|
|
}
|
|
|
|
let Predicates = [HasStdExtZvfbfwma] in {
|
|
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmaccbf16", "PseudoVFWMACCBF16",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
}
|
|
|
|
multiclass VPatConversionVI_VF_BF16<string intrinsic, string instruction> {
|
|
foreach fvti = AllBF16Vectors in {
|
|
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
|
|
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
|
|
GetVTypePredicates<ivti>.Predicates) in
|
|
defm : VPatConversion<intrinsic, instruction, "V",
|
|
ivti.Vector, fvti.Vector, ivti.Mask, fvti.Log2SEW,
|
|
fvti.LMul, ivti.RegClass, fvti.RegClass>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatConversionWF_VI_BF16<string intrinsic, string instruction,
|
|
bit isSEWAware = 0> {
|
|
foreach vtiToWti = AllWidenableIntToBF16Vectors in {
|
|
defvar vti = vtiToWti.Vti;
|
|
defvar fwti = vtiToWti.Wti;
|
|
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
|
|
GetVTypePredicates<fwti>.Predicates) in
|
|
defm : VPatConversion<intrinsic, instruction, "V",
|
|
fwti.Vector, vti.Vector, fwti.Mask, vti.Log2SEW,
|
|
vti.LMul, fwti.RegClass, vti.RegClass, isSEWAware>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatConversionWF_VF_BF16<string intrinsic, string instruction,
|
|
bit isSEWAware = 0> {
|
|
foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {
|
|
defvar fvti = fvtiToFWti.Vti;
|
|
defvar fwti = fvtiToFWti.Wti;
|
|
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
|
|
GetVTypeMinimalPredicates<fwti>.Predicates) in
|
|
defm : VPatConversion<intrinsic, instruction, "V",
|
|
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
|
|
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatConversionVI_WF_BF16<string intrinsic, string instruction> {
|
|
foreach vtiToWti = AllWidenableIntToBF16Vectors in {
|
|
defvar vti = vtiToWti.Vti;
|
|
defvar fwti = vtiToWti.Wti;
|
|
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
|
|
GetVTypePredicates<fwti>.Predicates) in
|
|
defm : VPatConversion<intrinsic, instruction, "W",
|
|
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
|
|
vti.LMul, vti.RegClass, fwti.RegClass>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatConversionVI_WF_RM_BF16<string intrinsic, string instruction> {
|
|
foreach vtiToWti = AllWidenableIntToBF16Vectors in {
|
|
defvar vti = vtiToWti.Vti;
|
|
defvar fwti = vtiToWti.Wti;
|
|
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
|
|
GetVTypePredicates<fwti>.Predicates) in
|
|
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
|
|
vti.Vector, fwti.Vector, vti.Mask, vti.Log2SEW,
|
|
vti.LMul, vti.RegClass, fwti.RegClass>;
|
|
}
|
|
}
|
|
|
|
multiclass VPatConversionVF_WF_BF16<string intrinsic, string instruction,
|
|
bit isSEWAware = 0> {
|
|
foreach fvtiToFWti = AllWidenableBF16ToFloatVectors in {
|
|
defvar fvti = fvtiToFWti.Vti;
|
|
defvar fwti = fvtiToFWti.Wti;
|
|
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
|
|
GetVTypePredicates<fwti>.Predicates) in
|
|
defm : VPatConversion<intrinsic, instruction, "W",
|
|
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
|
|
fvti.LMul, fvti.RegClass, fwti.RegClass, isSEWAware>;
|
|
}
|
|
}
|
|
|
|
let Predicates = [HasVInstructionsBF16] in {
|
|
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD_ALT",
|
|
AllBF16Vectors, isSEWAware = 1>;
|
|
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB_ALT",
|
|
AllBF16Vectors, isSEWAware = 1>;
|
|
defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB_ALT",
|
|
AllBF16Vectors, isSEWAware = 1>;
|
|
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwadd", "PseudoVFWADD_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwsub", "PseudoVFWSUB_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwadd_w", "PseudoVFWADD_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmacc", "PseudoVFMACC_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmacc", "PseudoVFNMACC_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsac", "PseudoVFMSAC_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsac", "PseudoVFNMSAC_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmadd", "PseudoVFMADD_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmadd", "PseudoVFNMADD_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsub", "PseudoVFMSUB_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsub", "PseudoVFNMSUB_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmacc", "PseudoVFWMACC_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmacc", "PseudoVFWNMACC_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwmsac", "PseudoVFWMSAC_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatUnaryV_V<"int_riscv_vfrsqrt7", "PseudoVFRSQRT7_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatUnaryV_V_RM<"int_riscv_vfrec7", "PseudoVFREC7_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnj", "PseudoVFSGNJ_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjn", "PseudoVFSGNJN_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryV_VV_VX<"int_riscv_vfsgnjx", "PseudoVFSGNJX_ALT",
|
|
AllBF16Vectors, isSEWAware=1>;
|
|
defm : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ_ALT", AllBF16Vectors>;
|
|
defm : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE_ALT", AllBF16Vectors>;
|
|
defm : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT_ALT", AllBF16Vectors>;
|
|
defm : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE_ALT", AllBF16Vectors>;
|
|
defm : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT_ALT", AllBF16Vectors>;
|
|
defm : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE_ALT", AllBF16Vectors>;
|
|
defm : VPatBinarySwappedM_VV<"int_riscv_vmfgt", "PseudoVMFLT_ALT", AllBF16Vectors>;
|
|
defm : VPatBinarySwappedM_VV<"int_riscv_vmfge", "PseudoVMFLE_ALT", AllBF16Vectors>;
|
|
defm : VPatConversionVI_VF_BF16<"int_riscv_vfclass", "PseudoVFCLASS_ALT">;
|
|
foreach vti = AllBF16Vectors in {
|
|
let Predicates = GetVTypePredicates<vti>.Predicates in
|
|
defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE_ALT",
|
|
"V"#vti.ScalarSuffix#"M",
|
|
vti.Vector,
|
|
vti.Vector, vti.Scalar, vti.Mask,
|
|
vti.Log2SEW, vti.LMul, vti.RegClass,
|
|
vti.RegClass, vti.ScalarRegClass>;
|
|
}
|
|
defm : VPatConversionWF_VI_BF16<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU_ALT",
|
|
isSEWAware=1>;
|
|
defm : VPatConversionWF_VI_BF16<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X_ALT",
|
|
isSEWAware=1>;
|
|
defm : VPatConversionWF_VF_BF16<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F_ALT",
|
|
isSEWAware=1>;
|
|
defm : VPatConversionVI_WF_RM_BF16<"int_riscv_vfncvt_xu_f_w", "PseudoVFNCVT_XU_F_ALT">;
|
|
defm : VPatConversionVI_WF_RM_BF16<"int_riscv_vfncvt_x_f_w", "PseudoVFNCVT_X_F_ALT">;
|
|
defm : VPatConversionVI_WF_BF16<"int_riscv_vfncvt_rtz_xu_f_w", "PseudoVFNCVT_RTZ_XU_F_ALT">;
|
|
defm : VPatConversionVI_WF_BF16<"int_riscv_vfncvt_rtz_x_f_w", "PseudoVFNCVT_RTZ_X_F_ALT">;
|
|
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F_ALT",
|
|
AllWidenableBF16ToFloatVectors, isSEWAware=1>;
|
|
defm : VPatConversionVF_WF_BF16<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F_ALT",
|
|
isSEWAware=1>;
|
|
defm : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP_ALT", AllBF16Vectors>;
|
|
defm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN_ALT", AllBF16Vectors>;
|
|
} // Predicates = [HasVInstructionsBF16]
|