derek.holloway
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209 lines
6.2 KiB
TableGen
209 lines
6.2 KiB
TableGen
//=== RISCVScheduleZvk.td - RISC-V Scheduling Definitions Zvk -*- tablegen ===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// Define scheduler resources associated with def operands.
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/// Zvbb extension
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defm "" : LMULSchedWrites<"WriteVBREVV">;
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defm "" : LMULSchedWrites<"WriteVCLZV">;
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defm "" : LMULSchedWrites<"WriteVCPOPV">;
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defm "" : LMULSchedWrites<"WriteVCTZV">;
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defm "" : LMULSchedWrites<"WriteVWSLLV">;
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defm "" : LMULSchedWrites<"WriteVWSLLX">;
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defm "" : LMULSchedWrites<"WriteVWSLLI">;
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/// Zvbc extension
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defm "" : LMULSchedWrites<"WriteVCLMULV">;
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defm "" : LMULSchedWrites<"WriteVCLMULX">;
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/// Zvkb extension
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// VANDN uses WriteVIALU[V|X|I]
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defm "" : LMULSchedWrites<"WriteVBREV8V">;
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defm "" : LMULSchedWrites<"WriteVREV8V">;
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defm "" : LMULSchedWrites<"WriteVRotV">;
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defm "" : LMULSchedWrites<"WriteVRotX">;
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defm "" : LMULSchedWrites<"WriteVRotI">;
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/// Zvkg extension
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defm "" : LMULSchedWrites<"WriteVGHSHV">;
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defm "" : LMULSchedWrites<"WriteVGMULV">;
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/// Zvknha or Zvknhb extensions
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defm "" : LMULSchedWrites<"WriteVSHA2CHV">;
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defm "" : LMULSchedWrites<"WriteVSHA2CLV">;
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defm "" : LMULSEWSchedWrites<"WriteVSHA2MSV">;
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/// Zvkned extension
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defm "" : LMULSchedWrites<"WriteVAESMVV">;
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defm "" : LMULSchedWrites<"WriteVAESKF1V">;
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defm "" : LMULSchedWrites<"WriteVAESKF2V">;
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defm "" : LMULSchedWrites<"WriteVAESZV">;
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/// Zvksed extension
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defm "" : LMULSchedWrites<"WriteVSM4KV">;
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defm "" : LMULSchedWrites<"WriteVSM4RV">;
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/// Zvksh extension
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defm "" : LMULSchedWrites<"WriteVSM3CV">;
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defm "" : LMULSchedWrites<"WriteVSM3MEV">;
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/// Define scheduler resources associated with use operands.
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/// Zvbb extension
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defm "" : LMULSchedReads<"ReadVBREVV">;
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defm "" : LMULSchedReads<"ReadVCLZV">;
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defm "" : LMULSchedReads<"ReadVCPOPV">;
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defm "" : LMULSchedReads<"ReadVCTZV">;
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defm "" : LMULSchedReads<"ReadVWSLLV">;
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defm "" : LMULSchedReads<"ReadVWSLLX">;
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/// Zvbc extension
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defm "" : LMULSchedReads<"ReadVCLMULV">;
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defm "" : LMULSchedReads<"ReadVCLMULX">;
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/// Zvkb extension
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// VANDN uses ReadVIALU[V|X|I]
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defm "" : LMULSchedReads<"ReadVBREV8V">;
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defm "" : LMULSchedReads<"ReadVREV8V">;
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defm "" : LMULSchedReads<"ReadVRotV">;
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defm "" : LMULSchedReads<"ReadVRotX">;
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/// Zvkg extension
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defm "" : LMULSchedReads<"ReadVGHSHV">;
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defm "" : LMULSchedReads<"ReadVGMULV">;
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/// Zvknha or Zvknhb extensions
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defm "" : LMULSchedReads<"ReadVSHA2CHV">;
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defm "" : LMULSchedReads<"ReadVSHA2CLV">;
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defm "" : LMULSEWSchedReads<"ReadVSHA2MSV">;
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/// Zvkned extension
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defm "" : LMULSchedReads<"ReadVAESMVV">;
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defm "" : LMULSchedReads<"ReadVAESKF1V">;
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defm "" : LMULSchedReads<"ReadVAESKF2V">;
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defm "" : LMULSchedReads<"ReadVAESZV">;
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/// Zvksed extension
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defm "" : LMULSchedReads<"ReadVSM4KV">;
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defm "" : LMULSchedReads<"ReadVSM4RV">;
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/// Zvksh extension
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defm "" : LMULSchedReads<"ReadVSM3CV">;
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defm "" : LMULSchedReads<"ReadVSM3MEV">;
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multiclass UnsupportedSchedZvbb {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVBREVV", []>;
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defm "" : LMULWriteRes<"WriteVCLZV", []>;
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defm "" : LMULWriteRes<"WriteVCPOPV", []>;
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defm "" : LMULWriteRes<"WriteVCTZV", []>;
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defm "" : LMULWriteRes<"WriteVWSLLV", []>;
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defm "" : LMULWriteRes<"WriteVWSLLX", []>;
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defm "" : LMULWriteRes<"WriteVWSLLI", []>;
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defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
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defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
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defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
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defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
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defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
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defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
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}
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}
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multiclass UnsupportedSchedZvbc {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVCLMULV", []>;
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defm "" : LMULWriteRes<"WriteVCLMULX", []>;
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defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
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defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
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}
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}
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multiclass UnsupportedSchedZvkb {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVBREV8V", []>;
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defm "" : LMULWriteRes<"WriteVREV8V", []>;
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defm "" : LMULWriteRes<"WriteVRotV", []>;
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defm "" : LMULWriteRes<"WriteVRotX", []>;
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defm "" : LMULWriteRes<"WriteVRotI", []>;
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defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
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defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
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defm "" : LMULReadAdvance<"ReadVRotV", 0>;
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defm "" : LMULReadAdvance<"ReadVRotX", 0>;
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}
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}
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multiclass UnsupportedSchedZvkg {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVGHSHV", []>;
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defm "" : LMULWriteRes<"WriteVGMULV", []>;
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defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
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defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
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}
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}
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multiclass UnsupportedSchedZvknhaOrZvknhb {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVSHA2CHV", []>;
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defm "" : LMULWriteRes<"WriteVSHA2CLV", []>;
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defm "" : LMULSEWWriteRes<"WriteVSHA2MSV", []>;
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defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
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defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
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defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;
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}
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}
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multiclass UnsupportedSchedZvkned {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVAESMVV", []>;
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defm "" : LMULWriteRes<"WriteVAESKF1V", []>;
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defm "" : LMULWriteRes<"WriteVAESKF2V", []>;
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defm "" : LMULWriteRes<"WriteVAESZV", []>;
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defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
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defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
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defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
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defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
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}
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}
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multiclass UnsupportedSchedZvksed {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVSM4KV", []>;
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defm "" : LMULWriteRes<"WriteVSM4RV", []>;
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defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
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defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
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}
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}
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multiclass UnsupportedSchedZvksh {
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let Unsupported = true in {
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defm "" : LMULWriteRes<"WriteVSM3CV", []>;
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defm "" : LMULWriteRes<"WriteVSM3MEV", []>;
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defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
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defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
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}
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}
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// Helper class to define all RISC-V Vector Crypto extensions as unsupported
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multiclass UnsupportedSchedZvk {
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defm "" : UnsupportedSchedZvbb;
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defm "" : UnsupportedSchedZvbc;
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defm "" : UnsupportedSchedZvkb;
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defm "" : UnsupportedSchedZvkg;
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defm "" : UnsupportedSchedZvknhaOrZvknhb;
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defm "" : UnsupportedSchedZvkned;
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defm "" : UnsupportedSchedZvksed;
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defm "" : UnsupportedSchedZvksh;
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}
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