derek.holloway
7502bf64a4
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62 lines
2.5 KiB
TableGen
62 lines
2.5 KiB
TableGen
/// Pattern Matchings for VEL intrinsic instructions.
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/// Intrinsic patterns written by hand.
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// Pack patterns.
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def : Pat<(i64 (int_ve_vl_pack_f32p ADDRrii:$addr0, ADDRrii:$addr1)),
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(ORrr (f2l (LDUrii MEMrii:$addr0)),
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(i2l (LDLZXrii MEMrii:$addr1)))>;
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def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
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(MULULrr
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(i2l (LDLZXrii MEMrii:$addr)),
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(LEASLrii (ANDrm (LEAzii 0, 0, (LO32 (i64 0x0000000100000001))),
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!add(32, 64)), 0,
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(HI32 (i64 0x0000000100000001))))>;
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// The extract/insert patterns.
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def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)),
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(EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>;
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def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)),
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(EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>;
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def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
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(INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>;
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def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
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(INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>;
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// VMRG patterns.
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def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
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(VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>;
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def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
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v256f64:$pt, i32:$vl),
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(VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl,
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v256f64:$pt)>;
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// VMV patterns.
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def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
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(VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>;
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def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
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(VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>;
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def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt,
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i32:$vl),
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(VMVrvml_v (i2l i32:$sy), v256f64:$vz, v256i1:$vm, i32:$vl,
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v256f64:$pt)>;
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// LSV patterns.
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def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
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(LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>;
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// LVS patterns.
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def : Pat<(int_ve_vl_lvsl_svs v256f64:$vx, i32:$sy),
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(LVSvr v256f64:$vx, (i2l i32:$sy))>;
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def : Pat<(int_ve_vl_lvsd_svs v256f64:$vx, i32:$sy),
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(LVSvr v256f64:$vx, (i2l i32:$sy))>;
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def : Pat<(int_ve_vl_lvss_svs v256f64:$vx, i32:$sy),
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(l2f (LVSvr v256f64:$vx, (i2l i32:$sy)))>;
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/// Intrinsic patterns automatically generated.
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include "VEInstrIntrinsicVL.gen.td"
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