derek.holloway
7502bf64a4
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542 lines
27 KiB
TableGen
542 lines
27 KiB
TableGen
//===---- X86InstrAMX.td - AMX Instruction Set Extension --*- tablegen -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel AMX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMX instructions
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multiclass AMX_TILE_COMMON<string Suffix, Predicate HasEGPR> {
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let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
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let hasSideEffects = 1,
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Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
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def LDTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
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"ldtilecfg\t$src",
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[(int_x86_ldtilecfg addr:$src)]>,
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T8, PS;
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let hasSideEffects = 1 in
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def STTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
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"sttilecfg\t$src",
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[(int_x86_sttilecfg addr:$src)]>,
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T8, PD;
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let mayLoad = 1 in
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def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
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(ins sibmem:$src),
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"tileloadd\t{$src, $dst|$dst, $src}", []>,
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T8, XD;
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let mayLoad = 1 in
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def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
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(ins sibmem:$src),
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"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
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T8, PD;
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let mayStore = 1 in
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def TILESTORED#Suffix : I<0x4b, MRMDestMemFSIB, (outs),
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(ins sibmem:$dst, TILE:$src),
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"tilestored\t{$src, $dst|$dst, $src}", []>,
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T8, XS;
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}
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}
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let SchedRW = [WriteSystem] in {
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defm "" : AMX_TILE_COMMON<"", NoEGPR>, VEX;
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defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>, EVEX, NoCD8;
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let Predicates = [HasAMXTILE, In64BitMode] in {
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let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
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def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
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"tilerelease", [(int_x86_tilerelease)]>, VEX, T8, PS;
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def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
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"tilezero\t$dst", []>,
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VEX, T8, XD;
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// Pseduo instruction for RA.
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let isPseudo = true, mayLoad = 1, hasSideEffects = 1,
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Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
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def PLDTILECFGV : PseudoI<(outs), (ins opaquemem:$src), []>;
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let isPseudo = true, mayLoad = 1 in
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def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2,
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opaquemem:$src3), []>;
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let isPseudo = true, mayLoad = 1 in
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def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2,
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opaquemem:$src3), []>;
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let isPseudo = true, mayStore = 1 in
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def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
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GR16:$src2, opaquemem:$src3,
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TILE:$src4), []>;
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let isPseudo = true, isReMaterializable = 1, isAsCheapAsAMove = 1,
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canFoldAsLoad = 1, usesCustomInserter = 1 in
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def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
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[(set TILE:$dst, (int_x86_tilezero_internal
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GR16:$src1, GR16:$src2))]>;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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let mayLoad = 1 in
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def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
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let mayLoad = 1 in
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def PTILELOADDT1 : PseudoI<(outs), (ins u8imm:$src1,
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sibmem:$src2), []>;
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let mayStore = 1 in
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def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>;
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def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
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[(int_x86_tilezero timm:$src)]>;
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}
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} // Predicates
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} // SchedRW
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let Predicates = [HasAMXINT8, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in {
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def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX, VVVV, T8, XD;
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def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX, VVVV, T8, XS;
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def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX, VVVV, T8, PD;
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def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
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VEX, VVVV, T8;
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}
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// Pseduo instruction for RA.
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let isPseudo = true, Constraints = "$src4 = $dst" in {
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def PTDPBSSDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbssd_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTDPBSUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbsud_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTDPBUSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbusd_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTDPBUUDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbuud_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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}
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbssd timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbsud timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbusd timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbuud timm:$src1,
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timm:$src2, timm:$src3)]>;
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}
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}
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} // HasAMXTILE
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let Predicates = [HasAMXBF16, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in
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def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, VEX, VVVV, T8, XS;
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// Pseduo instruction for RA.
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let isPseudo = true, Constraints = "$src4 = $dst" in
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def PTDPBF16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpbf16ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbf16ps timm:$src1,
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timm:$src2, timm:$src3)]>;
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}
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}
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} // HasAMXTILE, HasAMXBF16
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//AMX-FP16
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let Predicates = [HasAMXFP16, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in {
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def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tdpfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[]>, VEX, VVVV, T8, XD;
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}
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// Pseduo instruction for RA.
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let isPseudo = true, Constraints = "$src4 = $dst" in {
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def PTDPFP16PSV : PseudoI<(outs TILE: $dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tdpfp16ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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}
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let usesCustomInserter = 1 in {
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def PTDPFP16PS : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpfp16ps timm:$src1,
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timm:$src2, timm:$src3)]>;
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}
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}
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} // HasAMXTILE, HasAMXFP16
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let Predicates = [HasAMXCOMPLEX, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in {
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def TCMMIMFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[]>, T8, PD, VEX, VVVV;
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def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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"tcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[]>, VEX, VVVV, WIG, T8;
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} // Constraints = "$src1 = $dst"
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let Constraints = "$src4 = $dst" in {
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def PTCMMIMFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tcmmimfp16ps_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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def PTCMMRLFP16PSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6),
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[(set TILE: $dst,
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(int_x86_tcmmrlfp16ps_internal GR16:$src1, GR16:$src2,
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GR16:$src3, TILE:$src4, TILE:$src5, TILE:$src6))]>;
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}
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let usesCustomInserter = 1 in {
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def PTCMMIMFP16PS : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tcmmimfp16ps timm:$src1,
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timm:$src2, timm:$src3)]>;
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def PTCMMRLFP16PS : PseudoI<(outs), (ins u8imm:$src1,
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u8imm:$src2, u8imm:$src3),
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[(int_x86_tcmmrlfp16ps timm:$src1,
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timm:$src2, timm:$src3)]>;
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}
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} // SchedRW = [WriteSystem]
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}
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// AMX-FP8
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let Predicates = [HasAMXFP8, In64BitMode] in {
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let SchedRW = [WriteSystem] in {
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let Constraints = "$src1 = $dst" in {
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class AMX_FP8_BASE<bits<8> Opcode, string Opstr> :
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I<Opcode, MRMSrcReg4VOp3, (outs TILE:$dst),
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(ins TILE:$src1, TILE:$src2, TILE:$src3),
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!strconcat(Opstr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[]>, VEX, VVVV;
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}
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def TDPBF8PS : AMX_FP8_BASE<0xfd, "tdpbf8ps">, T_MAP5, PS;
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def TDPBHF8PS : AMX_FP8_BASE<0xfd, "tdpbhf8ps">, T_MAP5, XD;
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def TDPHBF8PS : AMX_FP8_BASE<0xfd, "tdphbf8ps">, T_MAP5, XS;
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def TDPHF8PS : AMX_FP8_BASE<0xfd, "tdphf8ps">, T_MAP5, PD;
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let usesCustomInserter = 1 in {
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// Pseudo instructions, using immediates instead of tile registers.
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// To be translated to the actual instructions in X86ISelLowering.cpp
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def PTDPBF8PS : PseudoI<(outs),
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(ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbf8ps timm:$src1, timm:$src2,
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timm:$src3)]>;
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def PTDPBHF8PS : PseudoI<(outs),
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(ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
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[(int_x86_tdpbhf8ps timm:$src1, timm:$src2,
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timm:$src3)]>;
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def PTDPHBF8PS : PseudoI<(outs),
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(ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
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[(int_x86_tdphbf8ps timm:$src1, timm:$src2,
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timm:$src3)]>;
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def PTDPHF8PS : PseudoI<(outs),
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(ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
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[(int_x86_tdphf8ps timm:$src1, timm:$src2,
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timm:$src3)]>;
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}
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let Constraints = "$src4 = $dst" in {
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def PTDPBF8PSV : PseudoI<(outs TILE:$dst),
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(ins GR16:$src1, GR16:$src2, GR16:$src3,
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TILE:$src4, TILE:$src5, TILE:$src6),
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[(set TILE:$dst,
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(int_x86_tdpbf8ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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def PTDPBHF8PSV : PseudoI<(outs TILE:$dst),
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(ins GR16:$src1, GR16:$src2, GR16:$src3,
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TILE:$src4, TILE:$src5, TILE:$src6),
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[(set TILE:$dst,
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(int_x86_tdpbhf8ps_internal GR16:$src1,
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GR16:$src2, GR16:$src3, TILE:$src4,
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TILE:$src5, TILE:$src6))]>;
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def PTDPHBF8PSV : PseudoI<(outs TILE:$dst),
|
|
(ins GR16:$src1, GR16:$src2, GR16:$src3,
|
|
TILE:$src4, TILE:$src5, TILE:$src6),
|
|
[(set TILE:$dst,
|
|
(int_x86_tdphbf8ps_internal GR16:$src1,
|
|
GR16:$src2, GR16:$src3, TILE:$src4,
|
|
TILE:$src5, TILE:$src6))]>;
|
|
def PTDPHF8PSV : PseudoI<(outs TILE:$dst),
|
|
(ins GR16:$src1, GR16:$src2, GR16:$src3,
|
|
TILE:$src4, TILE:$src5, TILE:$src6),
|
|
[(set TILE:$dst,
|
|
(int_x86_tdphf8ps_internal GR16:$src1,
|
|
GR16:$src2, GR16:$src3, TILE:$src4,
|
|
TILE:$src5, TILE:$src6))]>;
|
|
}
|
|
}
|
|
}
|
|
|
|
multiclass TILELOADDRS_Base<string suffix> {
|
|
def suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
|
|
"tileloaddrs\t{$src1, $dst|$dst, $src1}", []>, T8, XD;
|
|
def T1#suffix : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src1),
|
|
"tileloaddrst1\t{$src1, $dst|$dst, $src1}", []>, T8, PD;
|
|
}
|
|
|
|
let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in
|
|
defm TILELOADDRS : TILELOADDRS_Base<"">, VEX;
|
|
|
|
let Predicates = [HasAMXMOVRS, HasEGPR, In64BitMode], SchedRW = [WriteSystem] in
|
|
defm TILELOADDRS : TILELOADDRS_Base<"_EVEX">, EVEX, NoCD8;
|
|
|
|
let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
|
|
let isPseudo = true, mayLoad = 1 in {
|
|
def PTILELOADDRSV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
|
|
GR16:$src2,
|
|
opaquemem:$src3), []>;
|
|
def PTILELOADDRST1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
|
|
GR16:$src2,
|
|
opaquemem:$src3), []>;
|
|
}
|
|
|
|
let usesCustomInserter = 1, mayLoad = 1 in {
|
|
def PTILELOADDRS : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
|
|
def PTILELOADDRST1 : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
|
|
}
|
|
} // HasAMXMOVRS, In64BitMode
|
|
|
|
multiclass m_tcvtrowd2ps {
|
|
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
|
|
let SchedRW = [WriteSystem] in {
|
|
def rti : Ii8<0x7, MRMSrcReg, (outs VR512:$dst),
|
|
(ins TILE:$src1, i32u8imm:$src2),
|
|
"tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[]>, TA,XS, EVEX, EVEX_V512;
|
|
def rte : I<0x4A, MRMSrcReg4VOp3, (outs VR512:$dst),
|
|
(ins TILE:$src1, GR32:$src2),
|
|
"tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[]>, T8,XS, EVEX, VVVV, EVEX_V512;
|
|
}
|
|
} // HasAMXAVX512, HasAVX10_2, In64BitMode
|
|
}
|
|
|
|
defm TCVTROWD2PS : m_tcvtrowd2ps;
|
|
|
|
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
|
|
let SchedRW = [WriteSystem] in {
|
|
let usesCustomInserter = 1 in {
|
|
def PTCVTROWD2PSrti : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),
|
|
[(set VR512:$dst, (int_x86_tcvtrowd2psi timm:$src1, timm:$src2))]>;
|
|
def PTCVTROWD2PSrte : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, GR32:$src2),
|
|
[(set VR512:$dst, (int_x86_tcvtrowd2ps timm:$src1, GR32:$src2))]>;
|
|
}
|
|
|
|
def PTCVTROWD2PSrtiV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u6imm:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowd2ps_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, imm:$src4))]>;
|
|
def PTCVTROWD2PSrteV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowd2ps_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, GR32:$src4))]>;
|
|
def PTCVTROWPS2BF16HrtiV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u6imm:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, imm:$src4))]>;
|
|
def PTCVTROWPS2BF16HrteV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2bf16h_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, GR32:$src4))]>;
|
|
def PTCVTROWPS2BF16LrtiV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u6imm:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, imm:$src4))]>;
|
|
def PTCVTROWPS2BF16LrteV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2bf16l_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, GR32:$src4))]>;
|
|
def PTCVTROWPS2PHHrtiV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u6imm:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2phh_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, imm:$src4))]>;
|
|
def PTCVTROWPS2PHHrteV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2phh_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, GR32:$src4))]>;
|
|
def PTCVTROWPS2PHLrtiV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u6imm:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2phl_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, imm:$src4))]>;
|
|
def PTCVTROWPS2PHLrteV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tcvtrowps2phl_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, GR32:$src4))]>;
|
|
}
|
|
}
|
|
|
|
multiclass AMXAVX512_BASE<bits<8> Opcode1, bits<8> Opcode2, string Opstr,
|
|
Prefix P1, Prefix P2> {
|
|
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode], SchedRW = [WriteSystem] in {
|
|
let OpPrefix = P1 in
|
|
def rte : I<Opcode1, MRMSrcReg4VOp3, (outs VR512:$dst),
|
|
(ins TILE:$src1, GR32:$src2),
|
|
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[]>, EVEX, VVVV, EVEX_V512, T8;
|
|
let OpPrefix = P2 in
|
|
def rti : Ii8<Opcode2, MRMSrcReg, (outs VR512:$dst),
|
|
(ins TILE:$src1, i32u8imm:$src2),
|
|
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[]>, EVEX, EVEX_V512, TA;
|
|
let usesCustomInserter = 1 in {
|
|
def "P"#NAME#"rte" : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, GR32:$src2),
|
|
[(set VR512:$dst,
|
|
(!cast<Intrinsic>("int_x86_"#Opstr) timm:$src1, GR32:$src2))]>;
|
|
def "P"#NAME#"rti" : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),
|
|
[(set VR512:$dst,
|
|
(!cast<Intrinsic>("int_x86_"#Opstr#"i") timm:$src1, timm:$src2))]>;
|
|
}
|
|
}
|
|
}
|
|
|
|
defm TCVTROWPS2PHH : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2phh", PS, PS>;
|
|
defm TCVTROWPS2PHL : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2phl", PD, XD>;
|
|
defm TCVTROWPS2BF16H : AMXAVX512_BASE<0x6d, 0x07, "tcvtrowps2bf16h", XD, XD>;
|
|
defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>;
|
|
|
|
multiclass AMXAVX512_TILEMOVE<bits<8> Opcode1, bits<8> Opcode2, string Opstr> {
|
|
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
|
|
let SchedRW = [WriteSystem] in {
|
|
def rti : Ii8<Opcode1, MRMSrcReg, (outs VR512:$dst),
|
|
(ins TILE:$src1, u8imm:$src2),
|
|
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[]>, TA, PD, EVEX, EVEX_V512;
|
|
def rte : I<Opcode2, MRMSrcReg4VOp3, (outs VR512:$dst),
|
|
(ins TILE:$src1, GR32:$src2),
|
|
!strconcat(Opstr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[]>, T8, PD, EVEX, VVVV, EVEX_V512;
|
|
}
|
|
} // HasAMXAVX512, HasAVX10_2, In64BitMode
|
|
}
|
|
|
|
defm TILEMOVROW : AMXAVX512_TILEMOVE<0x07, 0x4A, "tilemovrow">;
|
|
|
|
let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in {
|
|
let SchedRW = [WriteSystem] in {
|
|
let usesCustomInserter = 1 in {
|
|
def PTILEMOVROWrti : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2),
|
|
[(set VR512:$dst, (int_x86_tilemovrowi timm:$src1, timm:$src2))]>;
|
|
def PTILEMOVROWrte : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, GR32:$src2),
|
|
[(set VR512:$dst, (int_x86_tilemovrow timm:$src1, GR32:$src2))]>;
|
|
}
|
|
|
|
def PTILEMOVROWrtiV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, i32u6imm:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tilemovrow_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, imm:$src4))]>;
|
|
def PTILEMOVROWrteV : PseudoI<(outs VR512:$dst),
|
|
(ins GR16:$src1, GR16:$src2, TILE:$src3, GR32:$src4),
|
|
[(set VR512: $dst,
|
|
(int_x86_tilemovrow_internal GR16:$src1, GR16:$src2,
|
|
TILE:$src3, GR32:$src4))]>;
|
|
}
|
|
}
|
|
|
|
let Predicates = [HasAMXTF32, In64BitMode] in {
|
|
let SchedRW = [WriteSystem] in {
|
|
let Constraints = "$src1 = $dst" in {
|
|
def TMMULTF32PS: I<0x48, MRMSrcReg4VOp3, (outs TILE:$dst),
|
|
(ins TILE:$src1, TILE:$src2, TILE:$src3),
|
|
"tmmultf32ps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[]>, VEX, VVVV, T8, PD;
|
|
}
|
|
let Constraints = "$src4 = $dst" in {
|
|
def PTMMULTF32PSV : PseudoI<(outs TILE:$dst),
|
|
(ins GR16:$src1, GR16:$src2, GR16:$src3,
|
|
TILE:$src4, TILE:$src5, TILE:$src6),
|
|
[(set TILE:$dst,
|
|
(int_x86_tmmultf32ps_internal GR16:$src1,
|
|
GR16:$src2, GR16:$src3, TILE:$src4,
|
|
TILE:$src5, TILE:$src6))]>;
|
|
}
|
|
let usesCustomInserter = 1 in {
|
|
def PTMMULTF32PS : PseudoI<(outs),
|
|
(ins u8imm:$src1, u8imm:$src2, u8imm:$src3),
|
|
[(int_x86_tmmultf32ps timm:$src1, timm:$src2,
|
|
timm:$src3)]>;
|
|
}
|
|
} // SchedRW = [WriteSystem]
|
|
} // HasAMXTF32
|