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50 lines
2.1 KiB
TableGen
50 lines
2.1 KiB
TableGen
//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel RAO-INT
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// instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RAO-INT instructions
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def SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
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// RAO arithmetic instructions.
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// OUTCHAIN = AADD(INCHAIN, PTR, RHS)
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def X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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multiclass RaoInt<string m, string suffix = ""> {
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let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR32:$src2)] in
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def 32mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi32>;
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let Pattern = [(!cast<SDNode>("X86rao_" # m) addr:$src1, GR64:$src2)] in
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def 64mr#suffix : BinOpMR_M<0xfc, "a" # m, Xi64>;
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}
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let Predicates = [HasRAOINT, NoEGPR] in {
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defm AADD : RaoInt<"add">, T8;
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defm AAND : RaoInt<"and">, T8, PD;
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defm AOR : RaoInt<"or" >, T8, XD;
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defm AXOR : RaoInt<"xor">, T8, XS;
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}
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let Predicates = [HasRAOINT, HasEGPR, In64BitMode] in {
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defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4;
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defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD;
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defm AOR : RaoInt<"or", "_EVEX">, EVEX, T_MAP4, XD;
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defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS;
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}
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