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54 lines
2.9 KiB
LLVM
54 lines
2.9 KiB
LLVM
; RUN: opt %s -O2 -S | FileCheck %s
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; Check that llvm.x86.avx2.gather.d.ps.256 intrinsic is not eliminated as gather and store memory accesses are based on arr.ptr
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Function Attrs: nounwind readonly
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declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, ptr, <8 x i32>, <8 x float>, i8) #0
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; Function Attrs: nounwind
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define <8 x float> @foo1(ptr noalias %arr.ptr, ptr noalias readonly %vix.ptr, ptr noalias %t2.ptr) #1 {
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allocas:
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%vix = load <8 x i32>, ptr %vix.ptr, align 4
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%t1.ptr = getelementptr i8, ptr %arr.ptr, i8 4
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%v1 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #2
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store i8 1, ptr %t1.ptr, align 4
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%v2 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #2
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%res = fadd <8 x float> %v1, %v2
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ret <8 x float> %res
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}
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; CHECK: foo1
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; CHECK: llvm.x86.avx2.gather.d.ps.256
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; CHECK: store
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; CHECK: llvm.x86.avx2.gather.d.ps.256
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; Check that second gather is eliminated as gather and store memory accesses are based on different no-aliasing pointers
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; Function Attrs: nounwind
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define <8 x float> @foo2(ptr noalias readonly %arr.ptr, ptr noalias readonly %vix.ptr, ptr noalias %t2.ptr) #1 {
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allocas:
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%vix = load <8 x i32>, ptr %vix.ptr, align 4
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%t1.ptr = getelementptr i8, ptr %arr.ptr, i8 4
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%v1 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #2
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store i8 1, ptr %t2.ptr, align 4
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%v2 = tail call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> undef, ptr %arr.ptr, <8 x i32> %vix, <8 x float> <float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000, float 0xFFFFFFFFE0000000>, i8 1) #2
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%res = fadd <8 x float> %v1, %v2
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ret <8 x float> %res
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}
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; CHECK: foo2
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; CHECK: llvm.x86.avx2.gather.d.ps.256
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; CHECK: store
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; CHECK-NOT: llvm.x86.avx2.gather.d.ps.256
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attributes #0 = { nounwind readonly }
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attributes #1 = { nounwind "target-cpu"="corei7-avx" "target-features"="+avx2,+popcnt,+cmov,+f16c,+rdrnd,+fma" }
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attributes #2 = { nounwind }
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