derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
174 lines
12 KiB
LLVM
174 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
|
|
; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
|
|
; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=SIZE %s
|
|
; END.
|
|
|
|
define void @fneg_f16() {
|
|
; CHECK-LABEL: 'fneg_f16'
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
|
|
;
|
|
; SIZE-LABEL: 'fneg_f16'
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg half undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x half> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
|
|
;
|
|
%f16 = fneg half undef
|
|
%v2f16 = fneg <2 x half> undef
|
|
%v3f16 = fneg <3 x half> undef
|
|
%v4f16 = fneg <4 x half> undef
|
|
%v5f16 = fneg <5 x half> undef
|
|
%v8f16 = fneg <8 x half> undef
|
|
%v16f16 = fneg <16 x half> undef
|
|
%v17f16 = fneg <17 x half> undef
|
|
ret void
|
|
}
|
|
|
|
define void @fneg_bf16() {
|
|
; CHECK-LABEL: 'fneg_bf16'
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg bfloat undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x bfloat> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
|
|
;
|
|
; SIZE-LABEL: 'fneg_bf16'
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f16 = fneg bfloat undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f16 = fneg <2 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f16 = fneg <3 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f16 = fneg <4 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f16 = fneg <5 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f16 = fneg <8 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f16 = fneg <16 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v17f16 = fneg <17 x bfloat> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
|
|
;
|
|
%f16 = fneg bfloat undef
|
|
%v2f16 = fneg <2 x bfloat> undef
|
|
%v3f16 = fneg <3 x bfloat> undef
|
|
%v4f16 = fneg <4 x bfloat> undef
|
|
%v5f16 = fneg <5 x bfloat> undef
|
|
%v8f16 = fneg <8 x bfloat> undef
|
|
%v16f16 = fneg <16 x bfloat> undef
|
|
%v17f16 = fneg <17 x bfloat> undef
|
|
ret void
|
|
}
|
|
|
|
define void @fneg_f32() {
|
|
; CHECK-LABEL: 'fneg_f32'
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f32 = fneg <16 x float> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
|
|
;
|
|
; SIZE-LABEL: 'fneg_f32'
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f32 = fneg float undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f32 = fneg <2 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f32 = fneg <3 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f32 = fneg <4 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f32 = fneg <5 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f32 = fneg <8 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v9f32 = fneg <9 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f32 = fneg <16 x float> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
|
|
;
|
|
%f32 = fneg float undef
|
|
%v2f32 = fneg <2 x float> undef
|
|
%v3f32 = fneg <3 x float> undef
|
|
%v4f32 = fneg <4 x float> undef
|
|
%v5f32 = fneg <5 x float> undef
|
|
%v8f32 = fneg <8 x float> undef
|
|
%v9f32 = fneg <9 x float> undef
|
|
%v16f32 = fneg <16 x float> undef
|
|
ret void
|
|
}
|
|
|
|
define void @fneg_f64() {
|
|
; CHECK-LABEL: 'fneg_f64'
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f64 = fneg <8 x double> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f64 = fneg <16 x double> undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret void
|
|
;
|
|
; SIZE-LABEL: 'fneg_f64'
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f64 = fneg double undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v2f64 = fneg <2 x double> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v3f64 = fneg <3 x double> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v4f64 = fneg <4 x double> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v5f64 = fneg <5 x double> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v8f64 = fneg <8 x double> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %v16f64 = fneg <16 x double> undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
|
|
;
|
|
%f64 = fneg double undef
|
|
%v2f64 = fneg <2 x double> undef
|
|
%v3f64 = fneg <3 x double> undef
|
|
%v4f64 = fneg <4 x double> undef
|
|
%v5f64 = fneg <5 x double> undef
|
|
%v8f64 = fneg <8 x double> undef
|
|
%v16f64 = fneg <16 x double> undef
|
|
ret void
|
|
}
|
|
|
|
define i32 @fneg_idiom(i32 %arg) {
|
|
; CHECK-LABEL: 'fneg_idiom'
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> splat (float -0.000000e+00), undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> splat (float -0.000000e+00), undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> splat (float -0.000000e+00), undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %F64 = fsub double -0.000000e+00, undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = fsub <2 x double> splat (double -0.000000e+00), undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F64 = fsub <4 x double> splat (double -0.000000e+00), undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V8F64 = fsub <8 x double> splat (double -0.000000e+00), undef
|
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: ret i32 undef
|
|
;
|
|
; SIZE-LABEL: 'fneg_idiom'
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F32 = fsub float -0.000000e+00, undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fsub <4 x float> splat (float -0.000000e+00), undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fsub <8 x float> splat (float -0.000000e+00), undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = fsub <16 x float> splat (float -0.000000e+00), undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %F64 = fsub double -0.000000e+00, undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fsub <2 x double> splat (double -0.000000e+00), undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fsub <4 x double> splat (double -0.000000e+00), undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8F64 = fsub <8 x double> splat (double -0.000000e+00), undef
|
|
; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
|
|
;
|
|
%F32 = fsub float -0.0, undef
|
|
%V4F32 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, undef
|
|
%V8F32 = fsub <8 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
|
|
%V16F32 = fsub <16 x float> <float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0, float -0.0>, undef
|
|
|
|
%F64 = fsub double -0.0, undef
|
|
%V2F64 = fsub <2 x double> <double -0.0, double -0.0>, undef
|
|
%V4F64 = fsub <4 x double> <double -0.0, double -0.0, double -0.0, double -0.0>, undef
|
|
%V8F64 = fsub <8 x double> <double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0, double -0.0>, undef
|
|
|
|
ret i32 undef
|
|
}
|