derek.holloway
7502bf64a4
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95 lines
3.3 KiB
LLVM
95 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=gvn < %s | FileCheck %s
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@u = global i32 5, align 4
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@w = global i32 10, align 4
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define i32 @test_load() {
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; CHECK-LABEL: @test_load(
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; CHECK-NEXT: [[LV:%.*]] = load volatile i32, ptr @u, align 4
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; CHECK-NEXT: ret i32 [[LV]]
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;
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%l1 = load atomic i32, ptr @w unordered, align 4
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%lv = load volatile i32, ptr @u, align 4
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%l2 = load atomic i32, ptr @w unordered, align 4
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%res.1 = sub i32 %l1, %l2
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%res = add i32 %res.1, %lv
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ret i32 %res
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}
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define i32 @test_load_with_acquire_load() {
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; CHECK-LABEL: @test_load_with_acquire_load(
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; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w acquire, align 4
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; CHECK-NEXT: [[LV:%.*]] = load volatile i32, ptr @u, align 4
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; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w acquire, align 4
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; CHECK-NEXT: [[RES_1:%.*]] = sub i32 [[L1]], [[L2]]
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; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES_1]], [[LV]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%l1 = load atomic i32, ptr @w acquire, align 4
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%lv = load volatile i32, ptr @u, align 4
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%l2 = load atomic i32, ptr @w acquire, align 4
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%res.1 = sub i32 %l1, %l2
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%res = add i32 %res.1, %lv
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ret i32 %res
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}
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define i32 @test_load_with_seq_cst_load() {
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; CHECK-LABEL: @test_load_with_seq_cst_load(
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; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w seq_cst, align 4
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; CHECK-NEXT: [[LV:%.*]] = load volatile i32, ptr @u, align 4
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; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w seq_cst, align 4
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; CHECK-NEXT: [[RES_1:%.*]] = sub i32 [[L1]], [[L2]]
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; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES_1]], [[LV]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%l1 = load atomic i32, ptr @w seq_cst, align 4
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%lv = load volatile i32, ptr @u, align 4
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%l2 = load atomic i32, ptr @w seq_cst, align 4
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%res.1 = sub i32 %l1, %l2
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%res = add i32 %res.1, %lv
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ret i32 %res
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}
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define i32 @test_store(i32 %x) {
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; CHECK-LABEL: @test_store(
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; CHECK-NEXT: store volatile i32 [[X:%.*]], ptr @u, align 4
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; CHECK-NEXT: ret i32 0
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;
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%l1 = load atomic i32, ptr @w unordered, align 4
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store volatile i32 %x, ptr @u, align 4
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%l2 = load atomic i32, ptr @w unordered, align 4
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%res = sub i32 %l1, %l2
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ret i32 %res
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}
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define i32 @test_store_with_acquire_load(i32 %x) {
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; CHECK-LABEL: @test_store_with_acquire_load(
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; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w acquire, align 4
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; CHECK-NEXT: store volatile i32 [[X:%.*]], ptr @u, align 4
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; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w acquire, align 4
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; CHECK-NEXT: [[RES:%.*]] = sub i32 [[L1]], [[L2]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%l1 = load atomic i32, ptr @w acquire, align 4
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store volatile i32 %x, ptr @u, align 4
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%l2 = load atomic i32, ptr @w acquire, align 4
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%res = sub i32 %l1, %l2
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ret i32 %res
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}
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define i32 @test_store_with_seq_cst_load(i32 %x) {
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; CHECK-LABEL: @test_store_with_seq_cst_load(
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; CHECK-NEXT: [[L1:%.*]] = load atomic i32, ptr @w seq_cst, align 4
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; CHECK-NEXT: store volatile i32 [[X:%.*]], ptr @u, align 4
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; CHECK-NEXT: [[L2:%.*]] = load atomic i32, ptr @w seq_cst, align 4
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; CHECK-NEXT: [[RES:%.*]] = sub i32 [[L1]], [[L2]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%l1 = load atomic i32, ptr @w seq_cst, align 4
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store volatile i32 %x, ptr @u, align 4
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%l2 = load atomic i32, ptr @w seq_cst, align 4
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%res = sub i32 %l1, %l2
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ret i32 %res
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}
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