derek.holloway
7502bf64a4
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49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; REQUIRES: amdgpu-registered-target
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; RUN: llvm-as < %s | llvm-dis | FileCheck %s
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; Test assumed alignment parameter
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; CHECK: declare noundef nonnull align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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define ptr addrspace(4) @dispatch_ptr() {
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%ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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ret ptr addrspace(4) %ptr
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}
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; CHECK: declare i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) align 4 captures(none), i1 immarg) #1
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define i32 @ds_append(ptr addrspace(3) %ptr) {
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%ret = call i32 @llvm.amdgcn.ds.append.p3(ptr addrspace(3) %ptr, i1 false)
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ret i32 %ret
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}
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; Test assumed alignment parameter
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; CHECK: declare i32 @llvm.amdgcn.ds.consume.p3(ptr addrspace(3) align 4 captures(none), i1 immarg) #1
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define i32 @ds_consume(ptr addrspace(3) %ptr) {
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%ret = call i32 @llvm.amdgcn.ds.consume.p3(ptr addrspace(3) %ptr, i1 false)
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ret i32 %ret
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}
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; CHECK: declare void @llvm.amdgcn.s.wait.event(i16 immarg) #2
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define void @s_wait_event() {
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call void @llvm.amdgcn.s.wait.event(i16 0)
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ret void
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}
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; CHECK: declare void @llvm.amdgcn.s.wait.event.export.ready() #2
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define void @s_wait_event_export_ready() {
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call void @llvm.amdgcn.s.wait.event.export.ready()
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ret void
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}
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; Test assumed range
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; CHECK: declare noundef range(i32 32, 65) i32 @llvm.amdgcn.wavefrontsize() #0
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define i32 @wavefrontsize() {
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%ret = call i32 @llvm.amdgcn.wavefrontsize()
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ret i32 %ret
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}
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; CHECK: attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; CHECK: attributes #1 = { convergent nocallback nofree nounwind willreturn memory(argmem: readwrite) }
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; CHECK: attributes #2 = { nocallback nofree nounwind willreturn }
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