derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
53 lines
1.9 KiB
LLVM
53 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
|
|
|
|
; Check that DAGCombiner is not asserting with mis-matched vector element count, "Vector element counts must match in SIGN_EXTEND_INREG".
|
|
; Also no warning message of "warning: Possible incorrect use of EVT::getVectorNumElements() for scalable vector.".
|
|
|
|
define <vscale x 4 x i32> @sext_inreg(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: sext_inreg:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.s
|
|
; CHECK-NEXT: sxth z0.s, p0/m, z0.s
|
|
; CHECK-NEXT: ret
|
|
%sext = shl <vscale x 4 x i32> %a, splat(i32 16)
|
|
%conv = ashr <vscale x 4 x i32> %sext, splat(i32 16)
|
|
ret <vscale x 4 x i32> %conv
|
|
}
|
|
|
|
define <vscale x 4 x i32> @ashr_shl(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: ashr_shl:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: lsl z0.s, z0.s, #8
|
|
; CHECK-NEXT: asr z0.s, z0.s, #16
|
|
; CHECK-NEXT: ret
|
|
%shl = shl <vscale x 4 x i32> %a, splat(i32 8)
|
|
%r = ashr <vscale x 4 x i32> %shl, splat(i32 16)
|
|
ret <vscale x 4 x i32> %r
|
|
}
|
|
|
|
define <vscale x 4 x i32> @ashr_shl_illegal_trunc_vec_ty(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: ashr_shl_illegal_trunc_vec_ty:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: lsl z0.s, z0.s, #8
|
|
; CHECK-NEXT: asr z0.s, z0.s, #11
|
|
; CHECK-NEXT: ret
|
|
%shl = shl <vscale x 4 x i32> %a, splat(i32 8)
|
|
%r = ashr <vscale x 4 x i32> %shl, splat(i32 11)
|
|
ret <vscale x 4 x i32> %r
|
|
}
|
|
|
|
define <vscale x 4 x i32> @ashr_add_shl_nxv4i8(<vscale x 4 x i32> %a) {
|
|
; CHECK-LABEL: ashr_add_shl_nxv4i8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z1.s, #0x1000000
|
|
; CHECK-NEXT: lsl z0.s, z0.s, #24
|
|
; CHECK-NEXT: add z0.s, z0.s, z1.s
|
|
; CHECK-NEXT: asr z0.s, z0.s, #24
|
|
; CHECK-NEXT: ret
|
|
%conv = shl <vscale x 4 x i32> %a, splat(i32 24)
|
|
%sext = add <vscale x 4 x i32> %conv, splat(i32 16777216)
|
|
%conv1 = ashr <vscale x 4 x i32> %sext, splat(i32 24)
|
|
ret <vscale x 4 x i32> %conv1
|
|
}
|