derek.holloway
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120 lines
3.2 KiB
YAML
120 lines
3.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
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---
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name: test_rotr
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: test_rotr
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)
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; CHECK-NEXT: $w0 = COPY [[ROTR]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_FSHR %0, %0, %1(s32)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_rotl
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: test_rotl
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)
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; CHECK-NEXT: $w0 = COPY [[ROTL]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_FSHL %0, %0, %1(s32)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_vector_rotr
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: test_vector_rotr
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK-NEXT: [[ROTR:%[0-9]+]]:_(<4 x s32>) = G_ROTR [[COPY]], [[COPY1]](<4 x s32>)
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; CHECK-NEXT: $q0 = COPY [[ROTR]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s32>) = G_FSHR %0, %0, %1(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_vector_rotl
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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- { reg: '$w1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: test_vector_rotl
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK-NEXT: [[ROTL:%[0-9]+]]:_(<4 x s32>) = G_ROTL [[COPY]], [[COPY1]](<4 x s32>)
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; CHECK-NEXT: $q0 = COPY [[ROTL]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s32>) = G_FSHL %0, %0, %1(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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