derek.holloway
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93 lines
2.4 KiB
YAML
93 lines
2.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; CHECK-LABEL: name: s32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: %bitreverse:gpr32 = RBITWr %copy
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; CHECK-NEXT: $w0 = COPY %bitreverse
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%copy:gpr(i32) = COPY $w0
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%bitreverse:gpr(i32) = G_BITREVERSE %copy
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$w0 = COPY %bitreverse(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: s64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr64 = COPY $x0
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; CHECK-NEXT: %bitreverse:gpr64 = RBITXr %copy
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; CHECK-NEXT: $x0 = COPY %bitreverse
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%copy:gpr(i64) = COPY $x0
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%bitreverse:gpr(i64) = G_BITREVERSE %copy
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$x0 = COPY %bitreverse(i64)
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RET_ReallyLR implicit $x0
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...
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---
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name: v8s8_legal
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: v8s8_legal
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %vec:fpr64 = IMPLICIT_DEF
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; CHECK-NEXT: %bitreverse:fpr64 = RBITv8i8 %vec
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; CHECK-NEXT: $x0 = COPY %bitreverse
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%vec:fpr(<8 x i8>) = G_IMPLICIT_DEF
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%bitreverse:fpr(<8 x i8>) = G_BITREVERSE %vec
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$x0 = COPY %bitreverse(<8 x i8>)
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RET_ReallyLR implicit $x0
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...
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---
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name: v16s8_legal
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v16s8_legal
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %vec:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: %bitreverse:fpr128 = RBITv16i8 %vec
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; CHECK-NEXT: $q0 = COPY %bitreverse
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%vec:fpr(<16 x i8>) = G_IMPLICIT_DEF
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%bitreverse:fpr(<16 x i8>) = G_BITREVERSE %vec
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$q0 = COPY %bitreverse(<16 x i8>)
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RET_ReallyLR implicit $q0
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...
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