derek.holloway
7502bf64a4
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482 lines
16 KiB
YAML
482 lines
16 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: cmp_imm_32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: cmp_imm_32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i32) = G_CONSTANT i32 42
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%5:gpr(i32) = G_ICMP intpred(eq), %0(i32), %1
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$w0 = COPY %5(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_imm_64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: cmp_imm_64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i64) = COPY $x0
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%1:gpr(i64) = G_CONSTANT i64 42
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%5:gpr(i32) = G_ICMP intpred(eq), %0(i64), %1
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$w0 = COPY %5(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_imm_out_of_range
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: cmp_imm_out_of_range
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32
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; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i64) = COPY $x0
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%1:gpr(i64) = G_CONSTANT i64 13132
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%5:gpr(i32) = G_ICMP intpred(eq), %0(i64), %1
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$w0 = COPY %5(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_imm_lookthrough
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: cmp_imm_lookthrough
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i64) = G_CONSTANT i64 42
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%2:gpr(i32) = G_TRUNC %1(i64)
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%5:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
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$w0 = COPY %5(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_imm_lookthrough_bad_trunc
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(i32) = COPY $w0
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%1:gpr(i64) = G_CONSTANT i64 68719476736 ; 0x1000000000
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%2:gpr(i32) = G_TRUNC %1(i64) ; Value truncates to 0
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%5:gpr(i32) = G_ICMP intpred(eq), %0(i32), %2
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$w0 = COPY %5(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_neg_imm_32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: cmp_neg_imm_32
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr32sp = COPY $w0
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; CHECK-NEXT: [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri %reg0, 10, 0, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(i32) = COPY $w0
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%cst:gpr(i32) = G_CONSTANT i32 -10
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%cmp:gpr(i32) = G_ICMP intpred(eq), %reg0(i32), %cst
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$w0 = COPY %cmp(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_neg_imm_64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: cmp_neg_imm_64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
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; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %reg0, 10, 0, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(i64) = COPY $x0
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%cst:gpr(i64) = G_CONSTANT i64 -10
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%cmp:gpr(i32) = G_ICMP intpred(eq), %reg0(i64), %cst
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$w0 = COPY %cmp(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_neg_imm_invalid
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: cmp_neg_imm_invalid
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr32 = COPY $w0
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; CHECK-NEXT: %cst:gpr32 = MOVi32imm -5000
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %cst, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(i32) = COPY $w0
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%cst:gpr(i32) = G_CONSTANT i32 -5000
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%cmp:gpr(i32) = G_ICMP intpred(eq), %reg0(i32), %cst
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$w0 = COPY %cmp(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_arith_extended_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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; CHECK-LABEL: name: cmp_arith_extended_s64
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; CHECK: liveins: $w0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr32 = COPY $w0
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; CHECK-NEXT: %reg1:gpr64sp = COPY $x1
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; CHECK-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %reg1, %reg0, 18, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(i32) = COPY $w0
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%reg1:gpr(i64) = COPY $x1
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%ext:gpr(i64) = G_ZEXT %reg0(i32)
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%cst:gpr(i64) = G_CONSTANT i64 2
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%shift:gpr(i64) = G_SHL %ext, %cst(i64)
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%cmp:gpr(i32) = G_ICMP intpred(ugt), %reg1(i64), %shift
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$w0 = COPY %cmp(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_arith_extended_s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $h0
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; CHECK-LABEL: name: cmp_arith_extended_s32
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; CHECK: liveins: $w0, $w1, $h0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub
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; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: %reg1:gpr32sp = COPY $w1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0
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; CHECK-NEXT: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, [[COPY]], 10, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(i16) = COPY $h0
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%reg1:gpr(i32) = COPY $w1
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%ext:gpr(i32) = G_ZEXT %reg0(i16)
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%cst:gpr(i32) = G_CONSTANT i32 2
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%shift:gpr(i32) = G_SHL %ext, %cst(i32)
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%cmp:gpr(i32) = G_ICMP intpred(ugt), %reg1(i32), %shift
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$w0 = COPY %cmp(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_arith_extended_shl_too_large
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $x1
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; The constant on the G_SHL is > 4, so we won't sleect SUBSXrx
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; CHECK-LABEL: name: cmp_arith_extended_shl_too_large
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; CHECK: liveins: $w0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %reg0:gpr32 = COPY $w0
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; CHECK-NEXT: %reg1:gpr64 = COPY $x1
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; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0
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; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
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; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv
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; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %cmp
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%reg0:gpr(i32) = COPY $w0
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%reg1:gpr(i64) = COPY $x1
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%ext:gpr(i64) = G_ZEXT %reg0(i32)
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%cst:gpr(i64) = G_CONSTANT i64 5
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%shift:gpr(i64) = G_SHL %ext, %cst(i64)
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%cmp:gpr(i32) = G_ICMP intpred(ugt), %reg1(i64), %shift
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$w0 = COPY %cmp(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_add_rhs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; The CSINC should use the add's RHS.
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; CHECK-LABEL: name: cmp_add_rhs
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0
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; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1
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; CHECK-NEXT: %add_rhs:gpr32 = COPY $w2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
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; CHECK-NEXT: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %add
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%cmp_lhs:gpr(i32) = COPY $w0
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%cmp_rhs:gpr(i32) = COPY $w1
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%add_rhs:gpr(i32) = COPY $w2
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%cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i32), %cmp_rhs
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%add:gpr(i32) = G_ADD %cmp, %add_rhs
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$w0 = COPY %add(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_add_lhs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; The CSINC should use the add's LHS.
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; CHECK-LABEL: name: cmp_add_lhs
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0
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; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1
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; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
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; CHECK-NEXT: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv
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; CHECK-NEXT: $w0 = COPY %add
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%cmp_lhs:gpr(i32) = COPY $w0
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%cmp_rhs:gpr(i32) = COPY $w1
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%add_lhs:gpr(i32) = COPY $w2
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%cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i32), %cmp_rhs
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%add:gpr(i32) = G_ADD %add_lhs, %cmp
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$w0 = COPY %add(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_add_lhs_vector
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
|
|
|
|
; We don't emit CSINC with vectors, so there should be no optimization here.
|
|
|
|
; CHECK-LABEL: name: cmp_add_lhs_vector
|
|
; CHECK: liveins: $q0, $q1, $q2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %cmp_lhs:fpr128 = COPY $q0
|
|
; CHECK-NEXT: %cmp_rhs:fpr128 = COPY $q1
|
|
; CHECK-NEXT: %add_lhs:fpr128 = COPY $q2
|
|
; CHECK-NEXT: %cmp:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs
|
|
; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, %cmp
|
|
; CHECK-NEXT: $q0 = COPY %add
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%cmp_lhs:fpr(<4 x i32>) = COPY $q0
|
|
%cmp_rhs:fpr(<4 x i32>) = COPY $q1
|
|
%add_lhs:fpr(<4 x i32>) = COPY $q2
|
|
%cmp:fpr(<4 x i32>) = G_ICMP intpred(eq), %cmp_lhs(<4 x i32>), %cmp_rhs
|
|
%add:fpr(<4 x i32>) = G_ADD %add_lhs, %cmp
|
|
$q0 = COPY %add(<4 x i32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: cmp_add_rhs_64
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; The CSINC should use the add's RHS.
|
|
; CHECK-LABEL: name: cmp_add_rhs_64
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0
|
|
; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1
|
|
; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2
|
|
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
|
; CHECK-NEXT: %add:gpr64 = CSINCXr %add_rhs, %add_rhs, 1, implicit $nzcv
|
|
; CHECK-NEXT: $x0 = COPY %add
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%cmp_lhs:gpr(i64) = COPY $x0
|
|
%cmp_rhs:gpr(i64) = COPY $x1
|
|
%add_rhs:gpr(i64) = COPY $x2
|
|
%cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
|
|
%cmp_ext:gpr(i64) = G_ZEXT %cmp
|
|
%add:gpr(i64) = G_ADD %cmp_ext, %add_rhs
|
|
$x0 = COPY %add(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: cmp_add_rhs_64_zext_multi_use
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; The ZExt is used more than once so don't fold.
|
|
; CHECK-LABEL: name: cmp_add_rhs_64_zext_multi_use
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0
|
|
; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1
|
|
; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2
|
|
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
|
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
|
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0
|
|
; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
|
|
; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs
|
|
; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext
|
|
; CHECK-NEXT: $x0 = COPY %or
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%cmp_lhs:gpr(i64) = COPY $x0
|
|
%cmp_rhs:gpr(i64) = COPY $x1
|
|
%add_rhs:gpr(i64) = COPY $x2
|
|
%cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
|
|
%cmp_ext:gpr(i64) = G_ZEXT %cmp
|
|
%add:gpr(i64) = G_ADD %cmp_ext, %add_rhs
|
|
%or:gpr(i64) = G_OR %add, %cmp_ext
|
|
$x0 = COPY %or(i64)
|
|
RET_ReallyLR implicit $x0
|
|
|
|
...
|
|
---
|
|
name: cmp_add_rhs_64_cmp_multi_use
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0, $x1, $x2
|
|
|
|
; The cmp is used more than once so don't fold.
|
|
; CHECK-LABEL: name: cmp_add_rhs_64_cmp_multi_use
|
|
; CHECK: liveins: $x0, $x1, $x2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0
|
|
; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1
|
|
; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2
|
|
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
|
|
; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
|
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0
|
|
; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32
|
|
; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs
|
|
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], %cmp, %subreg.sub_32
|
|
; CHECK-NEXT: %cmp_ext2:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
|
|
; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext2
|
|
; CHECK-NEXT: $x0 = COPY %or
|
|
; CHECK-NEXT: RET_ReallyLR implicit $x0
|
|
%cmp_lhs:gpr(i64) = COPY $x0
|
|
%cmp_rhs:gpr(i64) = COPY $x1
|
|
%add_rhs:gpr(i64) = COPY $x2
|
|
%cmp:gpr(i32) = G_ICMP intpred(eq), %cmp_lhs(i64), %cmp_rhs
|
|
%cmp_ext:gpr(i64) = G_ZEXT %cmp
|
|
%add:gpr(i64) = G_ADD %cmp_ext, %add_rhs
|
|
%cmp_ext2:gpr(i64) = G_SEXT %cmp
|
|
%or:gpr(i64) = G_OR %add, %cmp_ext2
|
|
$x0 = COPY %or(i64)
|
|
RET_ReallyLR implicit $x0
|