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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-const-vector.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_constant_vec_pool_v2f64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_vec_pool_v2f64
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%3:fpr(s64) = G_FCONSTANT double 5.000000e-01
%2:fpr(s64) = G_FCONSTANT double 1.600000e+01
%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
RET_ReallyLR
...
---
name: test_constant_vec_pool_v4f32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_vec_pool_v4f32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%3:fpr(s32) = G_FCONSTANT float 5.000000e-01
%2:fpr(s32) = G_FCONSTANT float 1.600000e+01
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32)
G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
---
name: test_constant_vec_pool_v2i64
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_vec_pool_v2i64
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%3:gpr(s64) = G_CONSTANT i64 67839
%2:gpr(s64) = G_CONSTANT i64 12375
%1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64)
G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>))
RET_ReallyLR
...
---
name: test_constant_vec_pool_v4i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_vec_pool_v4i32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s128) from constant-pool)
; CHECK-NEXT: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%3:gpr(s32) = G_CONSTANT i32 67839
%2:gpr(s32) = G_CONSTANT i32 12375
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32)
G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
---
name: test_constant_vec_pool_v2i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_vec_pool_v2i32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 :: (load (s64) from constant-pool)
; CHECK-NEXT: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%3:gpr(s32) = G_CONSTANT i32 67839
%2:gpr(s32) = G_CONSTANT i32 12375
%1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32)
G_STORE %1(<2 x s32>), %0(p0) :: (store (<2 x s32>))
RET_ReallyLR
...
---
name: test_constant_all_zeros_v4f32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_all_zeros_v4f32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%2:fpr(s32) = G_FCONSTANT float 0.000000e+00
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
---
name: test_constant_all_ones_v4f32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_constant_all_ones_v4f32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 255
; CHECK-NEXT: STRQui [[MOVIv2d_ns]], [[COPY]], 0 :: (store (<4 x s32>))
; CHECK-NEXT: RET_ReallyLR
%0:gpr(p0) = COPY $x0
%2:fpr(s32) = G_FCONSTANT float 0xFFFFFFFFE0000000
%1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32)
G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>))
RET_ReallyLR
...
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