TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/select-modf.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
---
name:            test_modf_fp128
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
frameInfo:
  maxAlignment:    16
stack:
  - { id: 0, size: 16, alignment: 16 }
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: test_modf_fp128
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $q0 = COPY [[COPY]]
    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
    ; CHECK-NEXT: BL &modfl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $x0, implicit-def $q0
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
    ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui %stack.0, 0 :: (load (s128) from %stack.0)
    ; CHECK-NEXT: $q0 = COPY [[COPY1]]
    ; CHECK-NEXT: $q1 = COPY [[LDRQui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
    %0:fpr(s128) = COPY $q0
    %3:gpr(p0) = G_FRAME_INDEX %stack.0
    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    $q0 = COPY %0(s128)
    $x0 = COPY %3(p0)
    BL &modfl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $x0, implicit-def $q0
    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    %1:fpr(s128) = COPY $q0
    %2:fpr(s128) = G_LOAD %3(p0) :: (load (s128) from %stack.0)
    $q0 = COPY %1(s128)
    $q1 = COPY %2(s128)
    RET_ReallyLR implicit $q0, implicit $q1
...
---
name:            test_modf_double
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$d0' }
frameInfo:
  maxAlignment:    8
stack:
  - { id: 0, size: 8, alignment: 8 }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: test_modf_double
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $d0 = COPY [[COPY]]
    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
    ; CHECK-NEXT: BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui %stack.0, 0 :: (load (s64) from %stack.0)
    ; CHECK-NEXT: $d0 = COPY [[COPY1]]
    ; CHECK-NEXT: $d1 = COPY [[LDRDui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
    %0:fpr(s64) = COPY $d0
    %3:gpr(p0) = G_FRAME_INDEX %stack.0
    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    $d0 = COPY %0(s64)
    $x0 = COPY %3(p0)
    BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    %1:fpr(s64) = COPY $d0
    %2:fpr(s64) = G_LOAD %3(p0) :: (load (s64) from %stack.0)
    $d0 = COPY %1(s64)
    $d1 = COPY %2(s64)
    RET_ReallyLR implicit $d0, implicit $d1
...
---
name:            test_modf_double_vec
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$d0' }
frameInfo:
  maxAlignment:    8
stack:
  - { id: 0, size: 8, alignment: 8 }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: test_modf_double_vec
    ; CHECK: liveins: $d0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri %stack.0, 0, 0
    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: $d0 = COPY [[COPY]]
    ; CHECK-NEXT: $x0 = COPY [[ADDXri]]
    ; CHECK-NEXT: BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
    ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui %stack.0, 0 :: (load (s64) from %stack.0)
    ; CHECK-NEXT: $d0 = COPY [[COPY1]]
    ; CHECK-NEXT: $d1 = COPY [[LDRDui]]
    ; CHECK-NEXT: RET_ReallyLR implicit $d0, implicit $d1
    %0:fpr(s64) = COPY $d0
    %3:gpr(p0) = G_FRAME_INDEX %stack.0
    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    $d0 = COPY %0(s64)
    $x0 = COPY %3(p0)
    BL &modf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $x0, implicit-def $d0
    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    %1:fpr(s64) = COPY $d0
    %2:fpr(s64) = G_LOAD %3(p0) :: (load (s64) from %stack.0)
    $d0 = COPY %1(s64)
    $d1 = COPY %2(s64)
    RET_ReallyLR implicit $d0, implicit $d1
...