derek.holloway
7502bf64a4
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212 lines
6.3 KiB
LLVM
212 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-- -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-- -global-isel -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; Verify that we can fold csneg/csel into csinc instruction.
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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; int csinc1 (int a, int b) { return !a ? b+3 : b+1; }
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define i32 @csinc1(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc1:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: add w8, w1, #3
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; CHECK-SD-NEXT: csinc w0, w8, w1, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc1:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #3 // =0x3
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w8, w8, wzr, eq
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 3, i32 1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc2 (int a, int b) { return a ? b+3 : b+1; }
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define i32 @csinc2(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc2:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: add w8, w1, #3
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; CHECK-SD-NEXT: csinc w0, w8, w1, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc2:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #3 // =0x3
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w8, w8, wzr, ne
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 1, i32 3
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc3 (int a, int b) { return !a ? b+1 : b-3; }
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define i32 @csinc3(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc3:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sub w8, w1, #3
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csinc w0, w8, w1, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc3:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #-3 // =0xfffffffd
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w8, w8, wzr, ne
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 1, i32 -3
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc4 (int a, int b) { return a ? b+1 : b-3; }
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define i32 @csinc4(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc4:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sub w8, w1, #3
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csinc w0, w8, w1, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc4:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #-3 // =0xfffffffd
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w8, w8, wzr, eq
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 -3, i32 1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc5 (int a, int b) { return a ? b+1 : b-4095; }
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define i32 @csinc5(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc5:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sub w8, w1, #4095
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csinc w0, w8, w1, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc5:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #-4095 // =0xfffff001
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w8, w8, wzr, eq
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 -4095, i32 1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc6 (int a, int b) { return a ? b+1 : b-4096; }
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define i32 @csinc6(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc6:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sub w8, w1, #1, lsl #12 // =4096
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csinc w0, w8, w1, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc6:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: mov w8, #-4096 // =0xfffff000
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w8, w8, wzr, eq
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 -4096, i32 1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; prevent larger constants (the add laid after csinc)
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; int csinc7 (int a, int b) { return a ? b+1 : b-4097; }
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define i32 @csinc7(i32 %a, i32 %b) {
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; CHECK-LABEL: csinc7:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #-4097 // =0xffffefff
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csinc w8, w8, wzr, eq
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; CHECK-NEXT: add w0, w8, w1
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; CHECK-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 -4097, i32 1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc8 (int a, int b) { return a ? b-1 : b+1; }
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define i32 @csinc8(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc8:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sub w8, w1, #1
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csinc w0, w8, w1, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc8:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: cset w8, ne
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; CHECK-GI-NEXT: sbfx w8, w8, #0, #1
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; CHECK-GI-NEXT: orr w8, w8, #0x1
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 1, i32 -1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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; int csinc9 (int a, int b) { return a ? b+1 : b-1; }
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define i32 @csinc9(i32 %a, i32 %b) {
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; CHECK-SD-LABEL: csinc9:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sub w8, w1, #1
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csinc w0, w8, w1, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: csinc9:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: cset w8, eq
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; CHECK-GI-NEXT: sbfx w8, w8, #0, #1
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; CHECK-GI-NEXT: orr w8, w8, #0x1
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; CHECK-GI-NEXT: add w0, w8, w1
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; CHECK-GI-NEXT: ret
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entry:
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%tobool.not = icmp eq i32 %a, 0
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%cond.v = select i1 %tobool.not, i32 -1, i32 1
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%cond = add nsw i32 %cond.v, %b
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ret i32 %cond
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}
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