derek.holloway
7502bf64a4
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32 lines
932 B
LLVM
32 lines
932 B
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-redzone | FileCheck %s
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define i32 @foo(i32 %a, i32 %b) nounwind ssp {
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; CHECK-LABEL: foo:
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; CHECK-NOT: sub sp, sp
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; CHECK: ret
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%x = alloca i32, align 4
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store i32 %a, ptr %a.addr, align 4
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store i32 %b, ptr %b.addr, align 4
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%tmp = load i32, ptr %a.addr, align 4
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%tmp1 = load i32, ptr %b.addr, align 4
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%add = add nsw i32 %tmp, %tmp1
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store i32 %add, ptr %x, align 4
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%tmp2 = load i32, ptr %x, align 4
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ret i32 %tmp2
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}
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; We disable red-zone if NEON is available because copies of Q-regs
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; require a spill/fill and dynamic allocation. But we only need to do
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; this when FP registers are enabled.
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define void @bar(fp128 %f) "target-features"="-fp-armv8" {
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; CHECK-LABEL: bar:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp x0, x1, [sp, #-16]
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; CHECK-NEXT: ret
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%ptr = alloca fp128
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store fp128 %f, ptr %ptr
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ret void
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}
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