derek.holloway
7502bf64a4
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71 lines
2.2 KiB
LLVM
71 lines
2.2 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
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define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK-LABEL: testShiftRightArith_v8i16:
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; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]
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; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
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entry:
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%a.addr = alloca <8 x i16>, align 16
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%b.addr = alloca <8 x i16>, align 16
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store <8 x i16> %a, ptr %a.addr, align 16
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store <8 x i16> %b, ptr %b.addr, align 16
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%0 = load <8 x i16>, ptr %a.addr, align 16
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%1 = load <8 x i16>, ptr %b.addr, align 16
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%shr = ashr <8 x i16> %0, %1
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ret <8 x i16> %shr
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}
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define <4 x i32> @testShiftRightArith_v4i32(<4 x i32> %a, <4 x i32> %b) #0 {
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; CHECK-LABEL: testShiftRightArith_v4i32:
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; CHECK: neg.4s [[REG3:v[0-9]+]], [[REG3]]
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; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
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entry:
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%a.addr = alloca <4 x i32>, align 32
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%b.addr = alloca <4 x i32>, align 32
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store <4 x i32> %a, ptr %a.addr, align 32
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store <4 x i32> %b, ptr %b.addr, align 32
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%0 = load <4 x i32>, ptr %a.addr, align 32
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%1 = load <4 x i32>, ptr %b.addr, align 32
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%shr = ashr <4 x i32> %0, %1
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ret <4 x i32> %shr
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}
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define <8 x i16> @testShiftRightLogical(<8 x i16> %a, <8 x i16> %b) #0 {
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; CHECK: testShiftRightLogical
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; CHECK: neg.8h [[REG5:v[0-9]+]], [[REG5]]
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; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
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entry:
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%a.addr = alloca <8 x i16>, align 16
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%b.addr = alloca <8 x i16>, align 16
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store <8 x i16> %a, ptr %a.addr, align 16
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store <8 x i16> %b, ptr %b.addr, align 16
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%0 = load <8 x i16>, ptr %a.addr, align 16
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%1 = load <8 x i16>, ptr %b.addr, align 16
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%shr = lshr <8 x i16> %0, %1
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ret <8 x i16> %shr
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}
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define <1 x i64> @sshr_v1i64(<1 x i64> %A) nounwind {
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; CHECK-LABEL: sshr_v1i64:
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; CHECK: sshr d0, d0, #42
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%tmp3 = ashr <1 x i64> %A, < i64 42 >
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ret <1 x i64> %tmp3
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}
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define <1 x i64> @cmlt_v1i64(<1 x i64> %A) nounwind {
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; CHECK-LABEL: cmlt_v1i64:
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; CHECK: cmlt d0, d0, #0
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%tmp3 = ashr <1 x i64> %A, < i64 63 >
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ret <1 x i64> %tmp3
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}
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define <1 x i64> @ushr_v1i64(<1 x i64> %A) nounwind {
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; CHECK-LABEL: ushr_v1i64:
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; CHECK: ushr d0, d0, #63
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%tmp3 = lshr <1 x i64> %A, < i64 63 >
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ret <1 x i64> %tmp3
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}
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attributes #0 = { nounwind }
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