derek.holloway
7502bf64a4
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134 lines
3.5 KiB
LLVM
134 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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define i32 @icmp_slt_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_slt_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x4
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; CHECK-NEXT: sbcs xzr, x1, x5
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; CHECK-NEXT: sbcs xzr, x2, x6
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; CHECK-NEXT: sbcs xzr, x3, x7
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: ret
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%c = icmp slt i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_sgt_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_sgt_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x4, x0
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; CHECK-NEXT: sbcs xzr, x5, x1
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; CHECK-NEXT: sbcs xzr, x6, x2
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; CHECK-NEXT: sbcs xzr, x7, x3
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; CHECK-NEXT: cset w0, lt
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; CHECK-NEXT: ret
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%c = icmp sgt i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_sle_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_sle_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x4, x0
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; CHECK-NEXT: sbcs xzr, x5, x1
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; CHECK-NEXT: sbcs xzr, x6, x2
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; CHECK-NEXT: sbcs xzr, x7, x3
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; CHECK-NEXT: cset w0, ge
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; CHECK-NEXT: ret
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%c = icmp sle i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_sge_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_sge_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x4
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; CHECK-NEXT: sbcs xzr, x1, x5
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; CHECK-NEXT: sbcs xzr, x2, x6
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; CHECK-NEXT: sbcs xzr, x3, x7
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; CHECK-NEXT: cset w0, ge
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; CHECK-NEXT: ret
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%c = icmp sge i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_ult_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_ult_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x4
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; CHECK-NEXT: sbcs xzr, x1, x5
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; CHECK-NEXT: sbcs xzr, x2, x6
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; CHECK-NEXT: sbcs xzr, x3, x7
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%c = icmp ult i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_ugt_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_ugt_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x4, x0
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; CHECK-NEXT: sbcs xzr, x5, x1
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; CHECK-NEXT: sbcs xzr, x6, x2
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; CHECK-NEXT: sbcs xzr, x7, x3
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%c = icmp ugt i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_ule_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_ule_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x4, x0
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; CHECK-NEXT: sbcs xzr, x5, x1
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; CHECK-NEXT: sbcs xzr, x6, x2
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; CHECK-NEXT: sbcs xzr, x7, x3
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; CHECK-NEXT: cset w0, hs
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; CHECK-NEXT: ret
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%c = icmp ule i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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define i32 @icmp_uge_i256(i256 %a, i256 %b) nounwind {
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; CHECK-LABEL: icmp_uge_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x4
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; CHECK-NEXT: sbcs xzr, x1, x5
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; CHECK-NEXT: sbcs xzr, x2, x6
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; CHECK-NEXT: sbcs xzr, x3, x7
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; CHECK-NEXT: cset w0, hs
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; CHECK-NEXT: ret
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%c = icmp uge i256 %a, %b
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%r = zext i1 %c to i32
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ret i32 %r
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}
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; Select based on i256 comparison
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define i256 @select_slt_i256(i256 %a, i256 %b, i256 %x, i256 %y) nounwind {
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; CHECK-LABEL: select_slt_i256:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, x4
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; CHECK-NEXT: add x8, sp, #32
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: sbcs xzr, x1, x5
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; CHECK-NEXT: sbcs xzr, x2, x6
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; CHECK-NEXT: sbcs xzr, x3, x7
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; CHECK-NEXT: csel x8, x9, x8, lt
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; CHECK-NEXT: ldp x0, x1, [x8]
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; CHECK-NEXT: ldp x2, x3, [x8, #16]
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; CHECK-NEXT: ret
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%c = icmp slt i256 %a, %b
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%r = select i1 %c, i256 %x, i256 %y
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ret i256 %r
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}
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