derek.holloway
7502bf64a4
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215 lines
6.3 KiB
LLVM
215 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=arm64-eabi -mattr=fullfp16,sve | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=arm64-eabi -mattr=fullfp16,sve -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; CHECK-GI: warning: Instruction selection used fallback path for divnxv4f32_2
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define float @divf32_2(float %a) nounwind {
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; CHECK-SD-LABEL: divf32_2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: fmov s1, #0.50000000
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; CHECK-SD-NEXT: fmul s0, s0, s1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf32_2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov s1, #2.00000000
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; CHECK-GI-NEXT: fdiv s0, s0, s1
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; CHECK-GI-NEXT: ret
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%r = fdiv float %a, 2.0
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ret float %r
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}
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define float @divf32_2_arcp(float %a) nounwind {
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; CHECK-SD-LABEL: divf32_2_arcp:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: fmov s1, #0.50000000
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; CHECK-SD-NEXT: fmul s0, s0, s1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf32_2_arcp:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov s1, #2.00000000
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; CHECK-GI-NEXT: fdiv s0, s0, s1
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; CHECK-GI-NEXT: ret
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%r = fdiv arcp float %a, 2.0
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ret float %r
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}
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define float @divf32_p75(float %a) nounwind {
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; CHECK-LABEL: divf32_p75:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, #0.75000000
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; CHECK-NEXT: fdiv s0, s0, s1
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; CHECK-NEXT: ret
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%r = fdiv float %a, 0.75
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ret float %r
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}
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define float @divf32_p75_arcp(float %a) nounwind {
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; CHECK-SD-LABEL: divf32_p75_arcp:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #43691 // =0xaaab
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; CHECK-SD-NEXT: movk w8, #16298, lsl #16
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; CHECK-SD-NEXT: fmov s1, w8
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; CHECK-SD-NEXT: fmul s0, s0, s1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf32_p75_arcp:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov s1, #0.75000000
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; CHECK-GI-NEXT: fdiv s0, s0, s1
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; CHECK-GI-NEXT: ret
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%r = fdiv arcp float %a, 0.75
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ret float %r
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}
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define half @divf16_2(half %a) nounwind {
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; CHECK-SD-LABEL: divf16_2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: fmov h1, #0.50000000
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; CHECK-SD-NEXT: fmul h0, h0, h1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf16_2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov h1, #2.00000000
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; CHECK-GI-NEXT: fdiv h0, h0, h1
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; CHECK-GI-NEXT: ret
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%r = fdiv half %a, 2.0
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ret half %r
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}
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define half @divf16_32768(half %a) nounwind {
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; CHECK-SD-LABEL: divf16_32768:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #30720 // =0x7800
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; CHECK-SD-NEXT: fmov h1, w8
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; CHECK-SD-NEXT: fdiv h0, h0, h1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf16_32768:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI5_0
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; CHECK-GI-NEXT: ldr h1, [x8, :lo12:.LCPI5_0]
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; CHECK-GI-NEXT: fdiv h0, h0, h1
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; CHECK-GI-NEXT: ret
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%r = fdiv half %a, 32768.0
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ret half %r
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}
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define half @divf16_32768_arcp(half %a) nounwind {
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; CHECK-SD-LABEL: divf16_32768_arcp:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #30720 // =0x7800
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; CHECK-SD-NEXT: fmov h1, w8
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; CHECK-SD-NEXT: fdiv h0, h0, h1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf16_32768_arcp:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI6_0
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; CHECK-GI-NEXT: ldr h1, [x8, :lo12:.LCPI6_0]
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; CHECK-GI-NEXT: fdiv h0, h0, h1
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; CHECK-GI-NEXT: ret
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%r = fdiv arcp half %a, 32768.0
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ret half %r
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}
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define double @divf64_2(double %a) nounwind {
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; CHECK-SD-LABEL: divf64_2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: fmov d1, #0.50000000
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; CHECK-SD-NEXT: fmul d0, d0, d1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divf64_2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov d1, #2.00000000
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; CHECK-GI-NEXT: fdiv d0, d0, d1
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; CHECK-GI-NEXT: ret
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%r = fdiv double %a, 2.0
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ret double %r
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}
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define <4 x float> @divv4f32_2(<4 x float> %a) nounwind {
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; CHECK-SD-LABEL: divv4f32_2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: movi v1.4s, #63, lsl #24
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; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divv4f32_2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v1.4s, #64, lsl #24
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; CHECK-GI-NEXT: fdiv v0.4s, v0.4s, v1.4s
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; CHECK-GI-NEXT: ret
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%r = fdiv <4 x float> %a, <float 2.0, float 2.0, float 2.0, float 2.0>
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ret <4 x float> %r
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}
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define <4 x float> @divv4f32_2_arcp(<4 x float> %a) nounwind {
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; CHECK-SD-LABEL: divv4f32_2_arcp:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: movi v1.4s, #63, lsl #24
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; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divv4f32_2_arcp:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v1.4s, #64, lsl #24
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; CHECK-GI-NEXT: fdiv v0.4s, v0.4s, v1.4s
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; CHECK-GI-NEXT: ret
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%r = fdiv arcp <4 x float> %a, <float 2.0, float 2.0, float 2.0, float 2.0>
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ret <4 x float> %r
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}
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define <4 x float> @divv4f32_3(<4 x float> %a) nounwind {
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; CHECK-LABEL: divv4f32_3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov v1.4s, #3.00000000
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; CHECK-NEXT: fdiv v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%r = fdiv <4 x float> %a, <float 3.0, float 3.0, float 3.0, float 3.0>
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ret <4 x float> %r
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}
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define <4 x float> @divv4f32_3_arcp(<4 x float> %a) nounwind {
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; CHECK-SD-LABEL: divv4f32_3_arcp:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #43691 // =0xaaab
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; CHECK-SD-NEXT: movk w8, #16042, lsl #16
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; CHECK-SD-NEXT: dup v1.4s, w8
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; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: divv4f32_3_arcp:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov v1.4s, #3.00000000
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; CHECK-GI-NEXT: fdiv v0.4s, v0.4s, v1.4s
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; CHECK-GI-NEXT: ret
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%r = fdiv arcp <4 x float> %a, <float 3.0, float 3.0, float 3.0, float 3.0>
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ret <4 x float> %r
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}
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define <4 x float> @divv4f32_24816(<4 x float> %a) nounwind {
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; CHECK-LABEL: divv4f32_24816:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI12_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]
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; CHECK-NEXT: fdiv v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%r = fdiv <4 x float> %a, <float 2.0, float 4.0, float 8.0, float 16.0>
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ret <4 x float> %r
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}
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define <vscale x 4 x float> @divnxv4f32_2(<vscale x 4 x float> %a) nounwind {
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; CHECK-LABEL: divnxv4f32_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: fmul z0.s, p0/m, z0.s, #0.5
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; CHECK-NEXT: ret
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%r = fdiv <vscale x 4 x float> %a, splat (float 2.0)
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ret <vscale x 4 x float> %r
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}
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