derek.holloway
7502bf64a4
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549 lines
14 KiB
LLVM
549 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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define i1 @lt8_u8(i8 %0) {
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; CHECK-LABEL: lt8_u8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0xf8
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = icmp ult i8 %0, 8
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ret i1 %2
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}
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define i1 @lt32_u8(i8 %0) {
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; CHECK-LABEL: lt32_u8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0xe0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = icmp ult i8 %0, 32
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ret i1 %2
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}
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define i1 @lt64_u8(i8 %0) {
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; CHECK-LABEL: lt64_u8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0xc0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = icmp ult i8 %0, 64
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ret i1 %2
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}
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define i1 @lt8_u32(i32 %0) {
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; CHECK-LABEL: lt8_u32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #8
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%2 = icmp ult i32 %0, 8
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ret i1 %2
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}
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define i1 @lt32_u32(i32 %0) {
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; CHECK-LABEL: lt32_u32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #32
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%2 = icmp ult i32 %0, 32
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ret i1 %2
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}
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define i1 @lt64_u32(i32 %0) {
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; CHECK-LABEL: lt64_u32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp w0, #64
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%2 = icmp ult i32 %0, 64
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ret i1 %2
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}
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define i1 @lt8_u64(i64 %0) {
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; CHECK-LABEL: lt8_u64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%2 = icmp ult i64 %0, 8
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ret i1 %2
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}
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define i1 @lt32_u64(i64 %0) {
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; CHECK-LABEL: lt32_u64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #32
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%2 = icmp ult i64 %0, 32
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ret i1 %2
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}
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define i1 @lt64_u64(i64 %0) {
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; CHECK-LABEL: lt64_u64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmp x0, #64
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%2 = icmp ult i64 %0, 64
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ret i1 %2
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}
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define i1 @lt8_u16_and_5(i8 %0) {
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; CHECK-LABEL: lt8_u16_and_5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = and i8 %0, 5
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%3 = icmp ult i8 %2, 16
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ret i1 %3
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}
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define i1 @lt8_u16_and_19(i8 %0) {
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; CHECK-LABEL: lt8_u16_and_19:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x10
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = and i8 %0, 19
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%3 = icmp ult i8 %2, 16
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ret i1 %3
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}
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define i1 @lt32_u16_and_7(i32 %0) {
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; CHECK-LABEL: lt32_u16_and_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: cmp w8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = and i32 %0, 7
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%3 = icmp ult i32 %2, 16
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ret i1 %3
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}
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define i1 @lt32_u16_and_21(i32 %0) {
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; CHECK-LABEL: lt32_u16_and_21:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst w0, #0x10
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = and i32 %0, 21
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%3 = icmp ult i32 %2, 16
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ret i1 %3
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}
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define i1 @lt64_u16_and_9(i64 %0) {
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; CHECK-LABEL: lt64_u16_and_9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = and i64 %0, 9
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%3 = icmp ult i64 %2, 16
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ret i1 %3
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}
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define i1 @lt64_u16_and_23(i64 %0) {
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; CHECK-LABEL: lt64_u16_and_23:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tst x0, #0x10
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%2 = and i64 %0, 23
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%3 = icmp ult i64 %2, 16
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ret i1 %3
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}
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define i1 @test_disjoint(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: tst w9, w8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp eq i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint2(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: tst w9, w8
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp sgt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint3(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: tst w9, w8
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp slt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint4(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: and w8, w9, w8
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: cset w8, lt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%5 = and i32 %3, %4
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%6 = icmp sle i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_inverse_4(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint_inverse_4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bic w8, w9, w8
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; CHECK-NEXT: cmp w8, #1
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; CHECK-NEXT: cset w8, lt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp sle i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_inverse(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bics wzr, w9, w8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp eq i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint2_inverse(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint2_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bics wzr, w9, w8
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp sgt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint3_inverse(i1 %0, i32 %1, i32 %2) {
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; CHECK-LABEL: test_disjoint3_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr w9, w2, #0x800000
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; CHECK-NEXT: lsl w8, w8, w1
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; CHECK-NEXT: bics wzr, w9, w8
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i32 %2, 8388608
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%4 = shl nuw i32 1, %1
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%not = xor i32 %4, -1
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%5 = and i32 %3, %not
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%6 = icmp slt i32 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: tst x9, x8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp eq i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint2_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint2_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: tst x9, x8
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp sgt i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint3_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint3_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: orr x9, x2, #0x80000000000000
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; CHECK-NEXT: lsl x8, x8, x1
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; CHECK-NEXT: tst x9, x8
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: orr w8, w0, w8
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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entry:
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%3 = or disjoint i64 %2, 36028797018963968
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%4 = shl nuw i64 1, %1
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%5 = and i64 %3, %4
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%6 = icmp slt i64 %5, 0
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%7 = select i1 %0, i1 true, i1 %6
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ret i1 %7
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}
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define i1 @test_disjoint4_64(i1 %0, i64 %1, i64 %2) {
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; CHECK-LABEL: test_disjoint4_64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #1 // =0x1
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|
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
|
; CHECK-NEXT: lsl x8, x8, x1
|
|
; CHECK-NEXT: and x8, x9, x8
|
|
; CHECK-NEXT: cmp x8, #1
|
|
; CHECK-NEXT: cset w8, lt
|
|
; CHECK-NEXT: orr w8, w0, w8
|
|
; CHECK-NEXT: and w0, w8, #0x1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%3 = or disjoint i64 %2, 36028797018963968
|
|
%4 = shl nuw i64 1, %1
|
|
%5 = and i64 %3, %4
|
|
%6 = icmp sle i64 %5, 0
|
|
%7 = select i1 %0, i1 true, i1 %6
|
|
ret i1 %7
|
|
}
|
|
|
|
define i1 @test_disjoint_inverse_4_64(i1 %0, i64 %1, i64 %2) {
|
|
; CHECK-LABEL: test_disjoint_inverse_4_64:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov w8, #1 // =0x1
|
|
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
|
; CHECK-NEXT: lsl x8, x8, x1
|
|
; CHECK-NEXT: bic x8, x9, x8
|
|
; CHECK-NEXT: cmp x8, #1
|
|
; CHECK-NEXT: cset w8, lt
|
|
; CHECK-NEXT: orr w8, w0, w8
|
|
; CHECK-NEXT: and w0, w8, #0x1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%3 = or disjoint i64 %2, 36028797018963968
|
|
%4 = shl nuw i64 1, %1
|
|
%not = xor i64 %4, -1
|
|
%5 = and i64 %3, %not
|
|
%6 = icmp sle i64 %5, 0
|
|
%7 = select i1 %0, i1 true, i1 %6
|
|
ret i1 %7
|
|
}
|
|
|
|
define i1 @test_disjoint_inverse_64(i1 %0, i64 %1, i64 %2) {
|
|
; CHECK-LABEL: test_disjoint_inverse_64:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov w8, #1 // =0x1
|
|
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
|
; CHECK-NEXT: lsl x8, x8, x1
|
|
; CHECK-NEXT: bics xzr, x9, x8
|
|
; CHECK-NEXT: cset w8, eq
|
|
; CHECK-NEXT: orr w8, w0, w8
|
|
; CHECK-NEXT: and w0, w8, #0x1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%3 = or disjoint i64 %2, 36028797018963968
|
|
%4 = shl nuw i64 1, %1
|
|
%not = xor i64 %4, -1
|
|
%5 = and i64 %3, %not
|
|
%6 = icmp eq i64 %5, 0
|
|
%7 = select i1 %0, i1 true, i1 %6
|
|
ret i1 %7
|
|
}
|
|
|
|
define i1 @test_disjoint2_inverse_64(i1 %0, i64 %1, i64 %2) {
|
|
; CHECK-LABEL: test_disjoint2_inverse_64:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov w8, #1 // =0x1
|
|
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
|
; CHECK-NEXT: lsl x8, x8, x1
|
|
; CHECK-NEXT: bics xzr, x9, x8
|
|
; CHECK-NEXT: cset w8, gt
|
|
; CHECK-NEXT: orr w8, w0, w8
|
|
; CHECK-NEXT: and w0, w8, #0x1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%3 = or disjoint i64 %2, 36028797018963968
|
|
%4 = shl nuw i64 1, %1
|
|
%not = xor i64 %4, -1
|
|
%5 = and i64 %3, %not
|
|
%6 = icmp sgt i64 %5, 0
|
|
%7 = select i1 %0, i1 true, i1 %6
|
|
ret i1 %7
|
|
}
|
|
|
|
define i1 @test_disjoint3_inverse_64(i1 %0, i64 %1, i64 %2) {
|
|
; CHECK-LABEL: test_disjoint3_inverse_64:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: mov w8, #1 // =0x1
|
|
; CHECK-NEXT: orr x9, x2, #0x80000000000000
|
|
; CHECK-NEXT: lsl x8, x8, x1
|
|
; CHECK-NEXT: bics xzr, x9, x8
|
|
; CHECK-NEXT: cset w8, mi
|
|
; CHECK-NEXT: orr w8, w0, w8
|
|
; CHECK-NEXT: and w0, w8, #0x1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%3 = or disjoint i64 %2, 36028797018963968
|
|
%4 = shl nuw i64 1, %1
|
|
%not = xor i64 %4, -1
|
|
%5 = and i64 %3, %not
|
|
%6 = icmp slt i64 %5, 0
|
|
%7 = select i1 %0, i1 true, i1 %6
|
|
ret i1 %7
|
|
}
|
|
|
|
; negative test
|
|
define i1 @lt3_u8(i8 %0) {
|
|
; CHECK-LABEL: lt3_u8:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: and w8, w0, #0xff
|
|
; CHECK-NEXT: cmp w8, #3
|
|
; CHECK-NEXT: cset w0, lo
|
|
; CHECK-NEXT: ret
|
|
%2 = icmp ult i8 %0, 3
|
|
ret i1 %2
|
|
}
|
|
|
|
; negative test
|
|
define i1 @lt3_u32(i32 %0) {
|
|
; CHECK-LABEL: lt3_u32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: cmp w0, #3
|
|
; CHECK-NEXT: cset w0, lo
|
|
; CHECK-NEXT: ret
|
|
%2 = icmp ult i32 %0, 3
|
|
ret i1 %2
|
|
}
|
|
|
|
; negative test
|
|
define i1 @lt3_u64(i64 %0) {
|
|
; CHECK-LABEL: lt3_u64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: cmp x0, #3
|
|
; CHECK-NEXT: cset w0, lo
|
|
; CHECK-NEXT: ret
|
|
%2 = icmp ult i64 %0, 3
|
|
ret i1 %2
|
|
}
|
|
|
|
; negative test
|
|
define i32 @lt32_u16_multiple_use(i32 %0) {
|
|
; CHECK-LABEL: lt32_u16_multiple_use:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #21 // =0x15
|
|
; CHECK-NEXT: mov w9, #10 // =0xa
|
|
; CHECK-NEXT: and w8, w0, w8
|
|
; CHECK-NEXT: cmp w8, #16
|
|
; CHECK-NEXT: orr w8, w8, w9
|
|
; CHECK-NEXT: cset w10, lo
|
|
; CHECK-NEXT: mul w0, w8, w10
|
|
; CHECK-NEXT: ret
|
|
%2 = and i32 %0, 21
|
|
%3 = icmp ult i32 %2, 16
|
|
%4 = add i32 %2, 10
|
|
%5 = zext i1 %3 to i32
|
|
%6 = mul i32 %4, %5
|
|
ret i32 %6
|
|
}
|