derek.holloway
7502bf64a4
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95 lines
3.4 KiB
LLVM
95 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -O3 -mtriple arm64-linux -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ASM
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; This test checks that nomerge correctly prevents the traps from being merged
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; in the compiled code.
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; Prior to ae6dc64ec670891cb15049277e43133d4df7fb4b, this test showed that
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; nomerge did not work correctly.
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@B = dso_local global [10 x i8] zeroinitializer, align 1
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@B2 = dso_local global [10 x i8] zeroinitializer, align 1
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; Function Attrs: noinline nounwind uwtable
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define dso_local void @f8(i32 noundef %i, i32 noundef %k) #0 {
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; CHECK-ASM-LABEL: f8:
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; CHECK-ASM: // %bb.0: // %entry
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; CHECK-ASM-NEXT: sub sp, sp, #16
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; CHECK-ASM-NEXT: .cfi_def_cfa_offset 16
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; CHECK-ASM-NEXT: .cfi_remember_state
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; CHECK-ASM-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-ASM-NEXT: sxtw x8, w0
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; CHECK-ASM-NEXT: stp w1, w0, [sp, #8]
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; CHECK-ASM-NEXT: cmp x8, #10
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; CHECK-ASM-NEXT: b.hi .LBB0_5
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; CHECK-ASM-NEXT: // %bb.1: // %entry
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; CHECK-ASM-NEXT: mov w9, #10 // =0xa
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; CHECK-ASM-NEXT: sub x9, x9, x8
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; CHECK-ASM-NEXT: cbz x9, .LBB0_5
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; CHECK-ASM-NEXT: // %bb.2:
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; CHECK-ASM-NEXT: ldrsw x9, [sp, #8]
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; CHECK-ASM-NEXT: adrp x10, .L_MergedGlobals
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; CHECK-ASM-NEXT: add x10, x10, :lo12:.L_MergedGlobals
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; CHECK-ASM-NEXT: strb wzr, [x10, x8]
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; CHECK-ASM-NEXT: cmp x9, #10
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; CHECK-ASM-NEXT: b.hi .LBB0_6
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; CHECK-ASM-NEXT: // %bb.3:
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; CHECK-ASM-NEXT: mov w8, #10 // =0xa
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; CHECK-ASM-NEXT: sub x8, x8, x9
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; CHECK-ASM-NEXT: cbz x8, .LBB0_6
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; CHECK-ASM-NEXT: // %bb.4:
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; CHECK-ASM-NEXT: add x8, x10, x9
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; CHECK-ASM-NEXT: strb wzr, [x8, #10]
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; CHECK-ASM-NEXT: add sp, sp, #16
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; CHECK-ASM-NEXT: .cfi_def_cfa_offset 0
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; CHECK-ASM-NEXT: ret
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; CHECK-ASM-NEXT: .LBB0_5: // %trap
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; CHECK-ASM-NEXT: .cfi_restore_state
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; CHECK-ASM-NEXT: brk #0x1
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; CHECK-ASM-NEXT: .LBB0_6: // %trap3
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; CHECK-ASM-NEXT: brk #0x1
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entry:
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%i.addr = alloca i32, align 4
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%k.addr = alloca i32, align 4
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store i32 %i, ptr %i.addr, align 4
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store i32 %k, ptr %k.addr, align 4
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%0 = load i32, ptr %i.addr, align 4
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%idxprom = sext i32 %0 to i64
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%1 = add i64 0, %idxprom
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%arrayidx = getelementptr inbounds [10 x i8], ptr @B, i64 0, i64 %idxprom
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%2 = sub i64 10, %1
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%3 = icmp ult i64 10, %1
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%4 = icmp ult i64 %2, 1
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%5 = or i1 %3, %4
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br i1 %5, label %trap, label %6
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6: ; preds = %entry
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store i8 0, ptr %arrayidx, align 1
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%7 = load i32, ptr %k.addr, align 4
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%idxprom1 = sext i32 %7 to i64
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%8 = add i64 0, %idxprom1
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%arrayidx2 = getelementptr inbounds [10 x i8], ptr @B2, i64 0, i64 %idxprom1
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%9 = sub i64 10, %8
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%10 = icmp ult i64 10, %8
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%11 = icmp ult i64 %9, 1
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%12 = or i1 %10, %11
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br i1 %12, label %trap3, label %13
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13: ; preds = %6
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store i8 0, ptr %arrayidx2, align 1
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ret void
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trap: ; preds = %entry
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call void @llvm.trap() #2
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unreachable
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trap3: ; preds = %6
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call void @llvm.trap() #2
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unreachable
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}
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; Function Attrs: cold noreturn nounwind memory(inaccessiblemem: write)
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declare void @llvm.trap() #1
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attributes #0 = { noinline nounwind uwtable }
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attributes #1 = { cold noreturn nounwind memory(inaccessiblemem: write) }
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attributes #2 = { noreturn nounwind nomerge }
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