derek.holloway
7502bf64a4
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57 lines
2.2 KiB
LLVM
57 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=aarch64 -mattr=+v8.9a -mattr=+sve -mattr=+rcpc3 < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64 -mattr=+v8.9a -mattr=+sve < %s | FileCheck %s
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; Show what happens with RCPC3 for extract/insert into SVE vectors.
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; Currently there is no RCPC3 codegen expected for this.
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define hidden <vscale x 2 x i64> @test_load_sve_lane0(ptr nocapture noundef readonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr {
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; CHECK-LABEL: test_load_sve_lane0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl1
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; CHECK-NEXT: ldapr x8, [x0]
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; CHECK-NEXT: mov z0.d, p0/m, x8
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; CHECK-NEXT: ret
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%1 = load atomic i64, ptr %a acquire, align 8
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%vldap1_lane = insertelement <vscale x 2 x i64> %b, i64 %1, i64 0
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ret <vscale x 2 x i64> %vldap1_lane
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}
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define hidden <vscale x 2 x i64> @test_load_sve_lane1(ptr nocapture noundef readonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr {
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; CHECK-LABEL: test_load_sve_lane1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: index z1.d, #0, #1
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov z2.d, x8
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; CHECK-NEXT: ldapr x8, [x0]
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; CHECK-NEXT: cmpeq p1.d, p0/z, z1.d, z2.d
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; CHECK-NEXT: mov z0.d, p1/m, x8
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; CHECK-NEXT: ret
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%1 = load atomic i64, ptr %a acquire, align 8
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%vldap1_lane = insertelement <vscale x 2 x i64> %b, i64 %1, i64 1
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ret <vscale x 2 x i64> %vldap1_lane
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}
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define hidden void @test_store_sve_lane0(ptr nocapture noundef writeonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr {
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; CHECK-LABEL: test_store_sve_lane0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: stlr x8, [x0]
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; CHECK-NEXT: ret
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%1 = extractelement <vscale x 2 x i64> %b, i64 0
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store atomic i64 %1, ptr %a release, align 8
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ret void
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}
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define hidden void @test_store_sve_lane1(ptr nocapture noundef writeonly %a, <vscale x 2 x i64> noundef %b) local_unnamed_addr {
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; CHECK-LABEL: test_store_sve_lane1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: stlr x8, [x0]
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; CHECK-NEXT: ret
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%1 = extractelement <vscale x 2 x i64> %b, i64 1
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store atomic i64 %1, ptr %a release, align 8
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ret void
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}
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