derek.holloway
7502bf64a4
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31 lines
1.5 KiB
LLVM
31 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple aarch64 -mcpu=tsv110 -mattr=+sve < %s | FileCheck %s
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; Check that the movprfx intrinsic does not prevent load instructions from
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; being scheduled together. As load instructions have long latency, expected
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; be preferentially issued.
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; NOTE: The unused paramter ensures z0/z1 is free, avoiding the antidependence for schedule.
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define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, ptr %base) {
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; CHECK-LABEL: and_i64_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: movprfx z0, z2
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; CHECK-NEXT: abs z0.d, p1/m, z2.d
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; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
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; CHECK-NEXT: add z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%data0 = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %c, i1 0)
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%data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr %base,
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i32 1,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %c)
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%out = add <vscale x 2 x i64> %data0, %data1
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ret <vscale x 2 x i64> %out
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}
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declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
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declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)
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