derek.holloway
7502bf64a4
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58 lines
2.5 KiB
LLVM
58 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefix=CHECK0
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -aarch64-stack-hazard-size=1024 | FileCheck %s --check-prefix=CHECK1024
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;; The following run lines check the default values for aarch64-stack-hazard-size/aarch64-streaming-hazard-size.
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;; When +sme,+sve is set the hazard size should default to 1024.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -mattr=+sve | FileCheck %s --check-prefix=CHECK1024
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;; The hazard size can still be overridden/disabled when +sme,+sve is set.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -mattr=+sve -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefix=CHECK0
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;; When +sme-fa64 is set alongside +sme,+sve the default hazard size should be 0.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme-fa64 -mattr=+sme -mattr=+sve | FileCheck %s --check-prefix=CHECK0
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;; When +sme is set (without +sve) the default hazard size should be 0.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme | FileCheck %s --check-prefix=CHECK0
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define i32 @spill_fpr_with_gpr_stack_object(i64 %d) "aarch64_pstate_sm_compatible" {
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; CHECK0-LABEL: spill_fpr_with_gpr_stack_object:
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; CHECK0: // %bb.0: // %entry
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; CHECK0-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
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; CHECK0-NEXT: .cfi_def_cfa_offset 16
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; CHECK0-NEXT: .cfi_offset b8, -16
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; CHECK0-NEXT: mov x8, x0
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; CHECK0-NEXT: mov w0, wzr
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; CHECK0-NEXT: //APP
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; CHECK0-NEXT: //NO_APP
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; CHECK0-NEXT: str x8, [sp, #8]
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; CHECK0-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
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; CHECK0-NEXT: ret
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;
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; CHECK1024-LABEL: spill_fpr_with_gpr_stack_object:
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; CHECK1024: // %bb.0: // %entry
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; CHECK1024-NEXT: sub sp, sp, #1040
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; CHECK1024-NEXT: str d8, [sp] // 8-byte Spill
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; CHECK1024-NEXT: str x29, [sp, #1032] // 8-byte Spill
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; CHECK1024-NEXT: sub sp, sp, #1040
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; CHECK1024-NEXT: .cfi_def_cfa_offset 2080
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; CHECK1024-NEXT: .cfi_offset w29, -8
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; CHECK1024-NEXT: .cfi_offset b8, -1040
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; CHECK1024-NEXT: mov x8, x0
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; CHECK1024-NEXT: mov w0, wzr
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; CHECK1024-NEXT: //APP
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; CHECK1024-NEXT: //NO_APP
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; CHECK1024-NEXT: str x8, [sp, #8]
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; CHECK1024-NEXT: add sp, sp, #1040
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; CHECK1024-NEXT: ldr x29, [sp, #1032] // 8-byte Reload
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; CHECK1024-NEXT: ldr d8, [sp] // 8-byte Reload
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; CHECK1024-NEXT: add sp, sp, #1040
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; CHECK1024-NEXT: ret
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entry:
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%a = alloca i64
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tail call void asm sideeffect "", "~{d8}"() #1
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store i64 %d, ptr %a
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ret i32 0
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}
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