derek.holloway
7502bf64a4
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32 lines
1.4 KiB
LLVM
32 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -debug-only=isel < %s 2>&1 | FileCheck %s
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; REQUIRES: asserts
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target triple = "aarch64-unknown-linux-gnu"
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; Ensure that only no offset frame indexes are folded into SVE load/stores when
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; accessing fixed width objects.
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define void @foo(ptr %a) #0 {
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; CHECK-LABEL: foo:
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; CHECK: SelectionDAG has 13 nodes:
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; CHECK-NEXT: t0: ch,glue = EntryToken
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; CHECK-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
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; CHECK-NEXT: t22: nxv2i64,ch = LDR_ZXI<Mem:(volatile load (<vscale x 1 x s128>) from %ir.a, align 64)> t2, TargetConstant:i64<0>, t0
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; CHECK-NEXT: t8: i64 = ADDXri TargetFrameIndex:i64<1>, TargetConstant:i32<0>, TargetConstant:i32<0>
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; CHECK-NEXT: t6: i64 = ADDXri TargetFrameIndex:i64<0>, TargetConstant:i32<0>, TargetConstant:i32<0>
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; CHECK-NEXT: t23: ch = STR_ZXI<Mem:(volatile store (<vscale x 1 x s128>) into %ir.r0, align 64)> t22, t6, TargetConstant:i64<0>, t22:1
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; CHECK-NEXT: t24: ch = STR_ZXI<Mem:(volatile store (<vscale x 1 x s128>) into %ir.r1, align 64)> t22, t8, TargetConstant:i64<0>, t23
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; CHECK-NEXT: t10: ch = RET_ReallyLR t24
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; CHECK-EMPTY:
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entry:
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%r0 = alloca <8 x i64>
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%r1 = alloca <8 x i64>
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%r = load volatile <8 x i64>, ptr %a
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store volatile <8 x i64> %r, ptr %r0
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store volatile <8 x i64> %r, ptr %r1
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ret void
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}
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attributes #0 = { nounwind "target-features"="+sve" vscale_range(4,4) }
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