derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
main
TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/sve-int-log.ll
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

724 lines
23 KiB
LLVM
Raw Permalink Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,SVE2
define <vscale x 2 x i64> @and_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: and_d:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = and <vscale x 2 x i64> %a, %b
ret <vscale x 2 x i64> %res
}
define <vscale x 4 x i32> @and_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: and_s:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = and <vscale x 4 x i32> %a, %b
ret <vscale x 4 x i32> %res
}
define <vscale x 8 x i16> @and_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: and_h:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = and <vscale x 8 x i16> %a, %b
ret <vscale x 8 x i16> %res
}
define <vscale x 16 x i8> @and_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: and_b:
; CHECK: // %bb.0:
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = and <vscale x 16 x i8> %a, %b
ret <vscale x 16 x i8> %res
}
define <vscale x 16 x i8> @and_b_zero(<vscale x 16 x i8> %a) {
; CHECK-LABEL: and_b_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: ret
%res = and <vscale x 16 x i8> %a, zeroinitializer
ret <vscale x 16 x i8> %res
}
define <vscale x 1 x i1> @and_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
; CHECK-LABEL: and_pred_q:
; CHECK: // %bb.0:
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = and <vscale x 1 x i1> %a, %b
ret <vscale x 1 x i1> %res
}
define <vscale x 2 x i1> @and_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
; CHECK-LABEL: and_pred_d:
; CHECK: // %bb.0:
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = and <vscale x 2 x i1> %a, %b
ret <vscale x 2 x i1> %res
}
define <vscale x 4 x i1> @and_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
; CHECK-LABEL: and_pred_s:
; CHECK: // %bb.0:
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = and <vscale x 4 x i1> %a, %b
ret <vscale x 4 x i1> %res
}
define <vscale x 8 x i1> @and_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
; CHECK-LABEL: and_pred_h:
; CHECK: // %bb.0:
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = and <vscale x 8 x i1> %a, %b
ret <vscale x 8 x i1> %res
}
define <vscale x 16 x i1> @and_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: and_pred_b:
; CHECK: // %bb.0:
; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = and <vscale x 16 x i1> %a, %b
ret <vscale x 16 x i1> %res
}
define <vscale x 2 x i64> @bic_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: bic_d:
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%not_b = xor <vscale x 2 x i64> %b, splat (i64 -1)
%res = and <vscale x 2 x i64> %a, %not_b
ret <vscale x 2 x i64> %res
}
define <vscale x 4 x i32> @bic_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: bic_s:
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%not_b = xor <vscale x 4 x i32> %b, splat (i32 -1)
%res = and <vscale x 4 x i32> %a, %not_b
ret <vscale x 4 x i32> %res
}
define <vscale x 8 x i16> @bic_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: bic_h:
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%not_b = xor <vscale x 8 x i16> %b, splat (i16 -1)
%res = and <vscale x 8 x i16> %a, %not_b
ret <vscale x 8 x i16> %res
}
define <vscale x 16 x i8> @bic_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: bic_b:
; CHECK: // %bb.0:
; CHECK-NEXT: bic z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%not_b = xor <vscale x 16 x i8> %b, splat (i8 -1)
%res = and <vscale x 16 x i8> %a, %not_b
ret <vscale x 16 x i8> %res
}
define <vscale x 1 x i1> @bic_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
; CHECK-LABEL: bic_pred_q:
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%not_b = xor <vscale x 1 x i1> %b, splat (i1 true)
%res = and <vscale x 1 x i1> %a, %not_b
ret <vscale x 1 x i1> %res
}
define <vscale x 2 x i1> @bic_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
; CHECK-LABEL: bic_pred_d:
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%not_b = xor <vscale x 2 x i1> %b, splat (i1 true)
%res = and <vscale x 2 x i1> %a, %not_b
ret <vscale x 2 x i1> %res
}
define <vscale x 4 x i1> @bic_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
; CHECK-LABEL: bic_pred_s:
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%not_b = xor <vscale x 4 x i1> %b, splat (i1 true)
%res = and <vscale x 4 x i1> %a, %not_b
ret <vscale x 4 x i1> %res
}
define <vscale x 8 x i1> @bic_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
; CHECK-LABEL: bic_pred_h:
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%not_b = xor <vscale x 8 x i1> %b, splat (i1 true)
%res = and <vscale x 8 x i1> %a, %not_b
ret <vscale x 8 x i1> %res
}
define <vscale x 16 x i1> @bic_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: bic_pred_b:
; CHECK: // %bb.0:
; CHECK-NEXT: bic p0.b, p0/z, p0.b, p1.b
; CHECK-NEXT: ret
%not_b = xor <vscale x 16 x i1> %b, splat (i1 true)
%res = and <vscale x 16 x i1> %a, %not_b
ret <vscale x 16 x i1> %res
}
define <vscale x 2 x i64> @or_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: or_d:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = or <vscale x 2 x i64> %a, %b
ret <vscale x 2 x i64> %res
}
define <vscale x 4 x i32> @or_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: or_s:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = or <vscale x 4 x i32> %a, %b
ret <vscale x 4 x i32> %res
}
define <vscale x 8 x i16> @or_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: or_h:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = or <vscale x 8 x i16> %a, %b
ret <vscale x 8 x i16> %res
}
define <vscale x 16 x i8> @or_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: or_b:
; CHECK: // %bb.0:
; CHECK-NEXT: orr z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = or <vscale x 16 x i8> %a, %b
ret <vscale x 16 x i8> %res
}
define <vscale x 16 x i8> @or_b_zero(<vscale x 16 x i8> %a) {
; CHECK-LABEL: or_b_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
%res = or <vscale x 16 x i8> %a, zeroinitializer
ret <vscale x 16 x i8> %res
}
define <vscale x 1 x i1> @or_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
; CHECK-LABEL: or_pred_q:
; CHECK: // %bb.0:
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
; CHECK-NEXT: ret
%res = or <vscale x 1 x i1> %a, %b
ret <vscale x 1 x i1> %res
}
define <vscale x 2 x i1> @or_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
; CHECK-LABEL: or_pred_d:
; CHECK: // %bb.0:
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
; CHECK-NEXT: ret
%res = or <vscale x 2 x i1> %a, %b
ret <vscale x 2 x i1> %res
}
define <vscale x 4 x i1> @or_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
; CHECK-LABEL: or_pred_s:
; CHECK: // %bb.0:
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
; CHECK-NEXT: ret
%res = or <vscale x 4 x i1> %a, %b
ret <vscale x 4 x i1> %res
}
define <vscale x 8 x i1> @or_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
; CHECK-LABEL: or_pred_h:
; CHECK: // %bb.0:
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
; CHECK-NEXT: ret
%res = or <vscale x 8 x i1> %a, %b
ret <vscale x 8 x i1> %res
}
define <vscale x 16 x i1> @or_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: or_pred_b:
; CHECK: // %bb.0:
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
; CHECK-NEXT: ret
%res = or <vscale x 16 x i1> %a, %b
ret <vscale x 16 x i1> %res
}
define <vscale x 2 x i64> @xor_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: xor_d:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = xor <vscale x 2 x i64> %a, %b
ret <vscale x 2 x i64> %res
}
define <vscale x 4 x i32> @xor_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: xor_s:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = xor <vscale x 4 x i32> %a, %b
ret <vscale x 4 x i32> %res
}
define <vscale x 8 x i16> @xor_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: xor_h:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = xor <vscale x 8 x i16> %a, %b
ret <vscale x 8 x i16> %res
}
define <vscale x 16 x i8> @xor_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: xor_b:
; CHECK: // %bb.0:
; CHECK-NEXT: eor z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%res = xor <vscale x 16 x i8> %a, %b
ret <vscale x 16 x i8> %res
}
define <vscale x 16 x i8> @xor_b_zero(<vscale x 16 x i8> %a) {
; CHECK-LABEL: xor_b_zero:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
%res = xor <vscale x 16 x i8> %a, zeroinitializer
ret <vscale x 16 x i8> %res
}
define <vscale x 1 x i1> @xor_pred_q(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {
; CHECK-LABEL: xor_pred_q:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.d
; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = xor <vscale x 1 x i1> %a, %b
ret <vscale x 1 x i1> %res
}
define <vscale x 2 x i1> @xor_pred_d(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) {
; CHECK-LABEL: xor_pred_d:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.d
; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = xor <vscale x 2 x i1> %a, %b
ret <vscale x 2 x i1> %res
}
define <vscale x 4 x i1> @xor_pred_s(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) {
; CHECK-LABEL: xor_pred_s:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.s
; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = xor <vscale x 4 x i1> %a, %b
ret <vscale x 4 x i1> %res
}
define <vscale x 8 x i1> @xor_pred_h(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) {
; CHECK-LABEL: xor_pred_h:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.h
; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = xor <vscale x 8 x i1> %a, %b
ret <vscale x 8 x i1> %res
}
define <vscale x 16 x i1> @xor_pred_b(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: xor_pred_b:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p2.b
; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
; CHECK-NEXT: ret
%res = xor <vscale x 16 x i1> %a, %b
ret <vscale x 16 x i1> %res
}
define void @array_and_not_nxv16i8(ptr %a, <vscale x 16 x i8> %m) {
; SVE-LABEL: array_and_not_nxv16i8:
; SVE: // %bb.0: // %entry
; SVE-NEXT: ptrue p0.b
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: rdvl x9, #1
; SVE-NEXT: .LBB39_1: // %vector.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ld1b { z1.b }, p0/z, [x0, x8]
; SVE-NEXT: bic z1.d, z1.d, z0.d
; SVE-NEXT: st1b { z1.b }, p0, [x0, x8]
; SVE-NEXT: add x8, x8, x9
; SVE-NEXT: cmp x8, #256
; SVE-NEXT: b.ne .LBB39_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_and_not_nxv16i8:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: ptrue p0.b
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: .LBB39_1: // %vector.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ld1b { z1.b }, p0/z, [x0, x8]
; SVE2-NEXT: bic z1.d, z1.d, z0.d
; SVE2-NEXT: st1b { z1.b }, p0, [x0, x8]
; SVE2-NEXT: incb x8
; SVE2-NEXT: cmp x8, #256
; SVE2-NEXT: b.ne .LBB39_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%not = xor <vscale x 16 x i8> %m, splat (i8 -1)
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 4
br label %vector.body
vector.body:
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%2 = getelementptr inbounds nuw i8, ptr %a, i64 %index
%wide.load = load <vscale x 16 x i8>, ptr %2, align 1
%3 = and <vscale x 16 x i8> %wide.load, %not
store <vscale x 16 x i8> %3, ptr %2, align 1
%index.next = add nuw i64 %index, %1
%4 = icmp eq i64 %index.next, 256
br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup:
ret void
}
define void @array_and_not_nxv8i16(ptr %a, <vscale x 8 x i16> %m) {
; SVE-LABEL: array_and_not_nxv8i16:
; SVE: // %bb.0: // %entry
; SVE-NEXT: ptrue p0.h
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: cnth x9
; SVE-NEXT: .LBB40_1: // %vector.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
; SVE-NEXT: bic z1.d, z1.d, z0.d
; SVE-NEXT: st1h { z1.h }, p0, [x0, x8, lsl #1]
; SVE-NEXT: add x8, x8, x9
; SVE-NEXT: cmp x8, #256
; SVE-NEXT: b.ne .LBB40_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_and_not_nxv8i16:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: ptrue p0.h
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: .LBB40_1: // %vector.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ld1h { z1.h }, p0/z, [x0, x8, lsl #1]
; SVE2-NEXT: bic z1.d, z1.d, z0.d
; SVE2-NEXT: st1h { z1.h }, p0, [x0, x8, lsl #1]
; SVE2-NEXT: inch x8
; SVE2-NEXT: cmp x8, #256
; SVE2-NEXT: b.ne .LBB40_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%not = xor <vscale x 8 x i16> %m, splat (i16 -1)
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 3
br label %vector.body
vector.body:
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%2 = getelementptr inbounds nuw i16, ptr %a, i64 %index
%wide.load = load <vscale x 8 x i16>, ptr %2, align 2
%3 = and <vscale x 8 x i16> %wide.load, %not
store <vscale x 8 x i16> %3, ptr %2, align 2
%index.next = add nuw i64 %index, %1
%4 = icmp eq i64 %index.next, 256
br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup:
ret void
}
define void @array_and_not_nxv4i32(ptr %a, <vscale x 4 x i32> %m) {
; SVE-LABEL: array_and_not_nxv4i32:
; SVE: // %bb.0: // %entry
; SVE-NEXT: ptrue p0.s
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: cntw x9
; SVE-NEXT: .LBB41_1: // %vector.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
; SVE-NEXT: bic z1.d, z1.d, z0.d
; SVE-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; SVE-NEXT: add x8, x8, x9
; SVE-NEXT: cmp x8, #256
; SVE-NEXT: b.ne .LBB41_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_and_not_nxv4i32:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: .LBB41_1: // %vector.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
; SVE2-NEXT: bic z1.d, z1.d, z0.d
; SVE2-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; SVE2-NEXT: incw x8
; SVE2-NEXT: cmp x8, #256
; SVE2-NEXT: b.ne .LBB41_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%not = xor <vscale x 4 x i32> %m, splat (i32 -1)
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 2
br label %vector.body
vector.body:
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%2 = getelementptr inbounds nuw i32, ptr %a, i64 %index
%wide.load = load <vscale x 4 x i32>, ptr %2, align 4
%3 = and <vscale x 4 x i32> %wide.load, %not
store <vscale x 4 x i32> %3, ptr %2, align 4
%index.next = add nuw i64 %index, %1
%4 = icmp eq i64 %index.next, 256
br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup:
ret void
}
define void @array_and_not_nxv2i64(ptr %a, <vscale x 2 x i64> %m) {
; SVE-LABEL: array_and_not_nxv2i64:
; SVE: // %bb.0: // %entry
; SVE-NEXT: ptrue p0.d
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: cntd x9
; SVE-NEXT: .LBB42_1: // %vector.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3]
; SVE-NEXT: bic z1.d, z1.d, z0.d
; SVE-NEXT: st1d { z1.d }, p0, [x0, x8, lsl #3]
; SVE-NEXT: add x8, x8, x9
; SVE-NEXT: cmp x8, #256
; SVE-NEXT: b.ne .LBB42_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_and_not_nxv2i64:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: ptrue p0.d
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: .LBB42_1: // %vector.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ld1d { z1.d }, p0/z, [x0, x8, lsl #3]
; SVE2-NEXT: bic z1.d, z1.d, z0.d
; SVE2-NEXT: st1d { z1.d }, p0, [x0, x8, lsl #3]
; SVE2-NEXT: incd x8
; SVE2-NEXT: cmp x8, #256
; SVE2-NEXT: b.ne .LBB42_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%not = xor <vscale x 2 x i64> %m, splat (i64 -1)
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 1
br label %vector.body
vector.body:
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%2 = getelementptr inbounds nuw i64, ptr %a, i64 %index
%wide.load = load <vscale x 2 x i64>, ptr %2, align 8
%3 = and <vscale x 2 x i64> %wide.load, %not
store <vscale x 2 x i64> %3, ptr %2, align 8
%index.next = add nuw i64 %index, %1
%4 = icmp eq i64 %index.next, 256
br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup:
ret void
}
define void @array_or_not_nxv4i32(ptr %a, <vscale x 4 x i32> %m) {
; SVE-LABEL: array_or_not_nxv4i32:
; SVE: // %bb.0: // %entry
; SVE-NEXT: subr z0.b, z0.b, #255 // =0xff
; SVE-NEXT: ptrue p0.s
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: cntw x9
; SVE-NEXT: .LBB43_1: // %vector.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
; SVE-NEXT: orr z1.d, z1.d, z0.d
; SVE-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; SVE-NEXT: add x8, x8, x9
; SVE-NEXT: cmp x8, #256
; SVE-NEXT: b.ne .LBB43_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_or_not_nxv4i32:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: subr z0.b, z0.b, #255 // =0xff
; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: .LBB43_1: // %vector.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
; SVE2-NEXT: orr z1.d, z1.d, z0.d
; SVE2-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; SVE2-NEXT: incw x8
; SVE2-NEXT: cmp x8, #256
; SVE2-NEXT: b.ne .LBB43_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%not = xor <vscale x 4 x i32> %m, splat (i32 -1)
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 2
br label %vector.body
vector.body:
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%2 = getelementptr inbounds nuw i32, ptr %a, i64 %index
%wide.load = load <vscale x 4 x i32>, ptr %2, align 4
%3 = or <vscale x 4 x i32> %wide.load, %not
store <vscale x 4 x i32> %3, ptr %2, align 4
%index.next = add nuw i64 %index, %1
%4 = icmp eq i64 %index.next, 256
br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup:
ret void
}
define void @array_xor_not_nxv4i32(ptr %a, <vscale x 4 x i32> %m) {
; SVE-LABEL: array_xor_not_nxv4i32:
; SVE: // %bb.0: // %entry
; SVE-NEXT: subr z0.b, z0.b, #255 // =0xff
; SVE-NEXT: ptrue p0.s
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: cntw x9
; SVE-NEXT: .LBB44_1: // %vector.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
; SVE-NEXT: eor z1.d, z1.d, z0.d
; SVE-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; SVE-NEXT: add x8, x8, x9
; SVE-NEXT: cmp x8, #256
; SVE-NEXT: b.ne .LBB44_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_xor_not_nxv4i32:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: ptrue p0.s
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: .LBB44_1: // %vector.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
; SVE2-NEXT: bsl2n z1.d, z1.d, z1.d, z0.d
; SVE2-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
; SVE2-NEXT: incw x8
; SVE2-NEXT: cmp x8, #256
; SVE2-NEXT: b.ne .LBB44_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%not = xor <vscale x 4 x i32> %m, splat (i32 -1)
%0 = tail call i64 @llvm.vscale.i64()
%1 = shl nuw nsw i64 %0, 2
br label %vector.body
vector.body:
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
%2 = getelementptr inbounds nuw i32, ptr %a, i64 %index
%wide.load = load <vscale x 4 x i32>, ptr %2, align 4
%3 = xor <vscale x 4 x i32> %wide.load, %not
store <vscale x 4 x i32> %3, ptr %2, align 4
%index.next = add nuw i64 %index, %1
%4 = icmp eq i64 %index.next, 256
br i1 %4, label %for.cond.cleanup, label %vector.body
for.cond.cleanup:
ret void
}
define void @array_xor_not_v4i32(ptr %a, <4 x i32> %m) {
; SVE-LABEL: array_xor_not_v4i32:
; SVE: // %bb.0: // %entry
; SVE-NEXT: mvn v0.16b, v0.16b
; SVE-NEXT: mov x8, xzr
; SVE-NEXT: .LBB45_1: // %for.body
; SVE-NEXT: // =>This Inner Loop Header: Depth=1
; SVE-NEXT: ldr q1, [x0, x8]
; SVE-NEXT: eor v1.16b, v1.16b, v0.16b
; SVE-NEXT: str q1, [x0, x8]
; SVE-NEXT: add x8, x8, #16
; SVE-NEXT: cmp x8, #1, lsl #12 // =4096
; SVE-NEXT: b.ne .LBB45_1
; SVE-NEXT: // %bb.2: // %for.cond.cleanup
; SVE-NEXT: ret
;
; SVE2-LABEL: array_xor_not_v4i32:
; SVE2: // %bb.0: // %entry
; SVE2-NEXT: mov x8, xzr
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
; SVE2-NEXT: .LBB45_1: // %for.body
; SVE2-NEXT: // =>This Inner Loop Header: Depth=1
; SVE2-NEXT: ldr q1, [x0, x8]
; SVE2-NEXT: bsl2n z1.d, z1.d, z1.d, z0.d
; SVE2-NEXT: str q1, [x0, x8]
; SVE2-NEXT: add x8, x8, #16
; SVE2-NEXT: cmp x8, #1, lsl #12 // =4096
; SVE2-NEXT: b.ne .LBB45_1
; SVE2-NEXT: // %bb.2: // %for.cond.cleanup
; SVE2-NEXT: ret
entry:
%invariant.op = xor <4 x i32> %m, splat (i32 -1)
br label %for.body
for.cond.cleanup:
ret void
for.body:
%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
%arrayidx = getelementptr inbounds nuw [16 x i8], ptr %a, i64 %indvars.iv
%0 = load <4 x i32>, ptr %arrayidx, align 16
%xor.reass.reass = xor <4 x i32> %0, %invariant.op
store <4 x i32> %xor.reass.reass, ptr %arrayidx, align 16
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond.not = icmp eq i64 %indvars.iv.next, 256
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
Reference in new issue View Git Blame Copy Permalink