derek.holloway
7502bf64a4
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115 lines
4.6 KiB
LLVM
115 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -enable-subreg-liveness -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
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; RUN: llc -enable-subreg-liveness -mattr=+sme -force-streaming < %s | FileCheck %s
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; RUN: llc -enable-subreg-liveness -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
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target triple = "aarch64"
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;
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; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
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; don't currently expect the code below to lower to BSL/BIT/BIF. Once
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; this is implemented, this test will be fleshed out.
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;
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define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) {
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; CHECK-LABEL: fixed_bitselect_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: ldp q5, q4, [x1]
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; CHECK-NEXT: ldp q6, q7, [x2]
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; CHECK-NEXT: movprfx z2, z1
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; CHECK-NEXT: subr z2.s, z2.s, #0 // =0x0
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; CHECK-NEXT: movprfx z3, z0
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; CHECK-NEXT: subr z3.s, z3.s, #0 // =0x0
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; CHECK-NEXT: sub z1.s, z1.s, #1 // =0x1
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; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x1
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; CHECK-NEXT: and z3.d, z3.d, z4.d
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; CHECK-NEXT: and z2.d, z2.d, z5.d
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; CHECK-NEXT: and z4.d, z0.d, z7.d
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; CHECK-NEXT: and z0.d, z1.d, z6.d
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; CHECK-NEXT: orr z0.d, z0.d, z2.d
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; CHECK-NEXT: orr z1.d, z4.d, z3.d
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: fixed_bitselect_v8i32:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
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; NONEON-NOSVE-NEXT: ldp q2, q3, [x1]
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; NONEON-NOSVE-NEXT: ldp q4, q5, [x2]
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; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #-128]!
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128
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; NONEON-NOSVE-NEXT: stp q1, q3, [sp, #48]
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; NONEON-NOSVE-NEXT: ldp w13, w11, [sp, #48]
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; NONEON-NOSVE-NEXT: ldp w14, w4, [sp, #64]
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; NONEON-NOSVE-NEXT: ldp w17, w16, [sp]
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; NONEON-NOSVE-NEXT: ldp w9, w8, [sp, #56]
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; NONEON-NOSVE-NEXT: neg w15, w11
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; NONEON-NOSVE-NEXT: neg w3, w13
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; NONEON-NOSVE-NEXT: str q4, [sp, #32]
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; NONEON-NOSVE-NEXT: and w14, w3, w14
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; NONEON-NOSVE-NEXT: and w15, w15, w4
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; NONEON-NOSVE-NEXT: neg w1, w17
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; NONEON-NOSVE-NEXT: ldp w5, w3, [sp, #72]
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; NONEON-NOSVE-NEXT: ldp w6, w4, [sp, #16]
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; NONEON-NOSVE-NEXT: ldp w12, w10, [sp, #8]
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; NONEON-NOSVE-NEXT: neg w2, w9
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; NONEON-NOSVE-NEXT: neg w7, w8
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; NONEON-NOSVE-NEXT: sub w17, w17, #1
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; NONEON-NOSVE-NEXT: and w2, w2, w5
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; NONEON-NOSVE-NEXT: and w1, w1, w6
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; NONEON-NOSVE-NEXT: and w3, w7, w3
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; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #24]
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; NONEON-NOSVE-NEXT: neg w0, w12
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; NONEON-NOSVE-NEXT: neg w7, w16
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; NONEON-NOSVE-NEXT: neg w18, w10
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; NONEON-NOSVE-NEXT: and w4, w7, w4
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; NONEON-NOSVE-NEXT: sub w10, w10, #1
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; NONEON-NOSVE-NEXT: sub w12, w12, #1
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; NONEON-NOSVE-NEXT: and w0, w0, w5
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; NONEON-NOSVE-NEXT: and w18, w18, w6
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; NONEON-NOSVE-NEXT: str q5, [sp, #80]
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; NONEON-NOSVE-NEXT: ldp w7, w5, [sp, #32]
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; NONEON-NOSVE-NEXT: sub w16, w16, #1
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; NONEON-NOSVE-NEXT: sub w8, w8, #1
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; NONEON-NOSVE-NEXT: sub w9, w9, #1
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; NONEON-NOSVE-NEXT: and w17, w17, w7
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; NONEON-NOSVE-NEXT: and w16, w16, w5
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; NONEON-NOSVE-NEXT: ldp w6, w7, [sp, #40]
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; NONEON-NOSVE-NEXT: and w12, w12, w6
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; NONEON-NOSVE-NEXT: and w10, w10, w7
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; NONEON-NOSVE-NEXT: orr w10, w10, w18
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; NONEON-NOSVE-NEXT: orr w12, w12, w0
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; NONEON-NOSVE-NEXT: ldp w18, w0, [sp, #88]
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; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #80]
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; NONEON-NOSVE-NEXT: stp w12, w10, [sp, #104]
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; NONEON-NOSVE-NEXT: sub w10, w11, #1
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; NONEON-NOSVE-NEXT: sub w11, w13, #1
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; NONEON-NOSVE-NEXT: and w8, w8, w0
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; NONEON-NOSVE-NEXT: and w9, w9, w18
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; NONEON-NOSVE-NEXT: orr w12, w16, w4
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; NONEON-NOSVE-NEXT: orr w8, w8, w3
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; NONEON-NOSVE-NEXT: orr w9, w9, w2
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; NONEON-NOSVE-NEXT: and w10, w10, w6
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; NONEON-NOSVE-NEXT: stp w9, w8, [sp, #120]
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; NONEON-NOSVE-NEXT: and w8, w11, w5
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; NONEON-NOSVE-NEXT: orr w13, w17, w1
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; NONEON-NOSVE-NEXT: orr w9, w10, w15
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; NONEON-NOSVE-NEXT: orr w8, w8, w14
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; NONEON-NOSVE-NEXT: stp w13, w12, [sp, #96]
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; NONEON-NOSVE-NEXT: stp w8, w9, [sp, #112]
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; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96]
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; NONEON-NOSVE-NEXT: add sp, sp, #128
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; NONEON-NOSVE-NEXT: ret
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%pre_cond = load <8 x i32>, ptr %pre_cond_ptr
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%left = load <8 x i32>, ptr %left_ptr
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%right = load <8 x i32>, ptr %right_ptr
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%neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
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%min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <8 x i32> %neg_cond, %left
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%right_bits_0 = and <8 x i32> %min_cond, %right
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%bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
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ret <8 x i32> %bsl0000
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}
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