derek.holloway
7502bf64a4
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65 lines
1.7 KiB
LLVM
65 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
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; We've got the usual issues with LLVM reordering blocks here. The
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; tests are correct for the current order, but who knows when that
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; will change. Beware!
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@var32 = global i32 0
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@var64 = global i64 0
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define i32 @test_tbz() {
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; CHECK-LABEL: test_tbz:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: Lloh0:
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; CHECK-NEXT: adrp x8, _var32@PAGE
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; CHECK-NEXT: Lloh1:
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; CHECK-NEXT: ldr w8, [x8, _var32@PAGEOFF]
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; CHECK-NEXT: tbz w8, #15, LBB0_5
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; CHECK-NEXT: ; %bb.1: ; %test1
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; CHECK-NEXT: tbz w8, #12, LBB0_5
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; CHECK-NEXT: ; %bb.2: ; %test2
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; CHECK-NEXT: Lloh2:
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; CHECK-NEXT: adrp x8, _var64@PAGE
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; CHECK-NEXT: Lloh3:
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; CHECK-NEXT: ldr x8, [x8, _var64@PAGEOFF]
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; CHECK-NEXT: tbz w8, #15, LBB0_5
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; CHECK-NEXT: ; %bb.3: ; %test3
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; CHECK-NEXT: tbz w8, #12, LBB0_5
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; CHECK-NEXT: ; %bb.4: ; %end2
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_5: ; %end1
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
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; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3
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%val = load i32, ptr @var32
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%val64 = load i64, ptr @var64
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%tbit0 = and i32 %val, 32768
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%tst0 = icmp ne i32 %tbit0, 0
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br i1 %tst0, label %test1, label %end1
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test1:
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%tbit1 = and i32 %val, 4096
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%tst1 = icmp ne i32 %tbit1, 0
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br i1 %tst1, label %test2, label %end1
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test2:
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%tbit2 = and i64 %val64, 32768
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%tst2 = icmp ne i64 %tbit2, 0
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br i1 %tst2, label %test3, label %end1
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test3:
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%tbit3 = and i64 %val64, 4096
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%tst3 = icmp ne i64 %tbit3, 0
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br i1 %tst3, label %end2, label %end1
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end2:
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ret i32 1
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end1:
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ret i32 0
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}
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