derek.holloway
7502bf64a4
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197 lines
6.5 KiB
LLVM
197 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 | FileCheck %s
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; Test for DAGCombiner optimization: fold (xor (smin(x, C), C)) -> select (x < C), xor (x, C), 0
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define i64 @test_smin_neg_one(i64 %a) {
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; CHECK-LABEL: test_smin_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmn x0, #1
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; CHECK-NEXT: csinv x0, xzr, x0, ge
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_smin_constant(i64 %a) {
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; CHECK-LABEL: test_smin_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, lt
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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; Test for DAGCombiner optimization: fold (xor (smax(x, C), C)) -> select (x > C), xor (x, C), 0
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define i64 @test_smax_neg_one(i64 %a) {
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; CHECK-LABEL: test_smax_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x8, x0
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; CHECK-NEXT: bic x0, x8, x0, asr #63
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_smax_constant(i64 %a) {
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; CHECK-LABEL: test_smax_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, gt
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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define i64 @test_umin_neg_one(i64 %a) {
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; CHECK-LABEL: test_umin_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x0, x0
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umin.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_umin_constant(i64 %a) {
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; CHECK-LABEL: test_umin_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, lo
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umin.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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define i64 @test_umax_neg_one(i64 %a) {
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; CHECK-LABEL: test_umax_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umax.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_umax_constant(i64 %a) {
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; CHECK-LABEL: test_umax_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, hi
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umax.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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; Test vector cases
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define <4 x i32> @test_smin_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_smin_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: cmgt v1.4s, v1.4s, v0.4s
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_smin_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_smin_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_smax_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_smax_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmge v1.4s, v0.4s, #0
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_smax_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_smax_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_umin_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_umin_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_umin_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_umin_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_umax_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_umax_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_umax_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_umax_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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declare i64 @llvm.smin.i64(i64, i64)
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declare i64 @llvm.smax.i64(i64, i64)
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declare i64 @llvm.umin.i64(i64, i64)
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declare i64 @llvm.umax.i64(i64, i64)
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declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
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