derek.holloway
7502bf64a4
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98 lines
3.6 KiB
LLVM
98 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s
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define amdgpu_kernel void @s_add_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
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; GFX11-LABEL: s_add_u64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_add_u32 s2, s2, s4
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; GFX11-NEXT: s_addc_u32 s3, s3, s5
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: s_add_u64:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_clause 0x1
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
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; GFX12-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_add_nc_u64 s[2:3], s[2:3], s[4:5]
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX12-NEXT: s_endpgm
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entry:
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%add = add i64 %a, %b
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store i64 %add, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @v_add_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
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; GCN-LABEL: v_add_u64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_add_co_ci_u32_e64 v3, null, v3, v5, vcc_lo
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; GCN-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GCN-NEXT: s_endpgm
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entry:
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%add = add i64 %a, %b
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store i64 %add, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_sub_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
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; GFX11-LABEL: s_sub_u64:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_sub_u32 s2, s2, s4
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; GFX11-NEXT: s_subb_u32 s3, s3, s5
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: s_sub_u64:
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; GFX12: ; %bb.0: ; %entry
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; GFX12-NEXT: s_clause 0x1
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
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; GFX12-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_sub_nc_u64 s[2:3], s[2:3], s[4:5]
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX12-NEXT: s_endpgm
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entry:
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%sub = sub i64 %a, %b
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store i64 %sub, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @v_sub_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
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; GCN-LABEL: v_sub_u64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_sub_co_u32 v2, vcc_lo, v2, v4
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_sub_co_ci_u32_e64 v3, null, v3, v5, vcc_lo
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; GCN-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GCN-NEXT: s_endpgm
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entry:
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%sub = sub i64 %a, %b
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store i64 %sub, ptr addrspace(1) %out
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ret void
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}
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