derek.holloway
7502bf64a4
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1213 lines
47 KiB
LLVM
1213 lines
47 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+flat-for-global -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s
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; Test atomicrmw min, max, umin, umax for global, flat, and local address spaces.
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; Address spaces: global(1), flat(0), local(3).
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@lds0 = internal addrspace(3) global [512 x i32] poison, align 4
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@lds1 = internal addrspace(3) global [512 x i64] poison, align 8
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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attributes #1 = { norecurse nounwind }
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;===----------------------------------------------------------------------===;
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; atomicrmw min
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;===----------------------------------------------------------------------===;
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define amdgpu_kernel void @global_atomic_min_ret_i32(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
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; GFX9-LABEL: global_atomic_min_ret_i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v0, 42
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_atomic_smin v0, v1, v0, s[2:3] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: buffer_wbinvl1_vol
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; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_atomic_min_ret_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v0, 42
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_atomic_smin v0, v1, v0, s[2:3] glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: buffer_gl1_inv
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; GFX10-NEXT: buffer_gl0_inv
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; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: global_atomic_min_ret_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_atomic_min_i32 v0, v1, v0, s[2:3] glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: buffer_gl1_inv
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; GFX11-NEXT: buffer_gl0_inv
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; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-NEXT: s_endpgm
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%result = atomicrmw min ptr addrspace(1) %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
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store i32 %result, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @global_atomic_min_ret_i64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
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; GFX9-LABEL: global_atomic_min_ret_i64:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v0, 42
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_atomic_smin_x2 v[0:1], v2, v[0:1], s[2:3] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: buffer_wbinvl1_vol
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; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: global_atomic_min_ret_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v0, 42
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: v_mov_b32_e32 v2, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_atomic_smin_x2 v[0:1], v2, v[0:1], s[2:3] glc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: buffer_gl1_inv
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; GFX10-NEXT: buffer_gl0_inv
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; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: global_atomic_min_ret_i64:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_atomic_min_i64 v[0:1], v2, v[0:1], s[2:3] glc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: buffer_gl1_inv
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; GFX11-NEXT: buffer_gl0_inv
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_endpgm
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%result = atomicrmw min ptr addrspace(1) %ptr, i64 42 syncscope("agent") seq_cst, align 8, !amdgpu.no.remote.memory !0
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store i64 %result, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_kernel void @flat_atomic_min_ret_i32(ptr addrspace(1) %out, ptr %ptr) #1 {
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; GFX9-LABEL: flat_atomic_min_ret_i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GFX9-NEXT: v_mov_b32_e32 v2, 42
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: v_mov_b32_e32 v1, s3
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; GFX9-NEXT: flat_atomic_smin v0, v[0:1], v2 glc
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; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX9-NEXT: buffer_wbinvl1_vol
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: flat_atomic_min_ret_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_add_u32 s12, s12, s17
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; GFX10-NEXT: s_addc_u32 s13, s13, 0
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v2, 42
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-NEXT: v_mov_b32_e32 v1, s3
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; GFX10-NEXT: flat_atomic_smin v0, v[0:1], v2 glc
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; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-NEXT: buffer_gl1_inv
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; GFX10-NEXT: buffer_gl0_inv
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: flat_atomic_min_ret_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX11-NEXT: v_mov_b32_e32 v2, 42
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
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; GFX11-NEXT: flat_atomic_min_i32 v0, v[0:1], v2 glc
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; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-NEXT: buffer_gl1_inv
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; GFX11-NEXT: buffer_gl0_inv
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; GFX11-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-NEXT: s_endpgm
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%result = atomicrmw min ptr %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
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store i32 %result, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @flat_atomic_min_ret_i64(ptr addrspace(1) %out, ptr %ptr) #1 {
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; GFX9-LABEL: flat_atomic_min_ret_i64:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GFX9-NEXT: v_mov_b32_e32 v0, 42
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v2, s2
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; GFX9-NEXT: v_mov_b32_e32 v3, s3
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; GFX9-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX9-NEXT: buffer_wbinvl1_vol
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: flat_atomic_min_ret_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_add_u32 s12, s12, s17
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; GFX10-NEXT: s_addc_u32 s13, s13, 0
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
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; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v0, 42
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v2, s2
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; GFX10-NEXT: v_mov_b32_e32 v3, s3
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; GFX10-NEXT: flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
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; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-NEXT: buffer_gl1_inv
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; GFX10-NEXT: buffer_gl0_inv
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; GFX10-NEXT: v_mov_b32_e32 v2, 0
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; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: flat_atomic_min_ret_i64:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
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; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
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; GFX11-NEXT: flat_atomic_min_i64 v[0:1], v[2:3], v[0:1] glc
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; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX11-NEXT: buffer_gl1_inv
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; GFX11-NEXT: buffer_gl0_inv
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_endpgm
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%result = atomicrmw min ptr %ptr, i64 42 syncscope("agent") seq_cst, align 8, !noalias.addrspace !1, !amdgpu.no.remote.memory !0
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store i64 %result, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_kernel void @local_atomic_min_ret_i32(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
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; GFX9-LABEL: local_atomic_min_ret_i32:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX9-NEXT: v_mov_b32_e32 v1, 42
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-NEXT: ds_min_rtn_i32 v0, v0, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: local_atomic_min_ret_i32:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
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; GFX10-NEXT: v_mov_b32_e32 v1, 42
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: ds_min_rtn_i32 v0, v0, v1
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: buffer_gl0_inv
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: local_atomic_min_ret_i32:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_dual_mov_b32 v1, 42 :: v_dual_mov_b32 v0, s0
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; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: ds_min_rtn_i32 v0, v0, v1
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: buffer_gl0_inv
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; GFX11-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
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; GFX11-NEXT: s_endpgm
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%result = atomicrmw min ptr addrspace(3) %ptr, i32 42 seq_cst, align 4
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store i32 %result, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @local_atomic_min_ret_i64(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
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; GFX9-LABEL: local_atomic_min_ret_i64:
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; GFX9: ; %bb.0:
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|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_min_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: local_atomic_min_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw min ptr addrspace(3) %ptr, i64 42 seq_cst, align 8
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
;===----------------------------------------------------------------------===;
|
|
; atomicrmw max
|
|
;===----------------------------------------------------------------------===;
|
|
|
|
define amdgpu_kernel void @global_atomic_max_ret_i32(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
|
|
; GFX9-LABEL: global_atomic_max_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_atomic_smax v0, v1, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: global_atomic_max_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_atomic_smax v0, v1, v0, s[2:3] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: global_atomic_max_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_atomic_max_i32 v0, v1, v0, s[2:3] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw max ptr addrspace(1) %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @global_atomic_max_ret_i64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
|
|
; GFX9-LABEL: global_atomic_max_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_atomic_smax_x2 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: global_atomic_max_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_atomic_smax_x2 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: global_atomic_max_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_atomic_max_i64 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw max ptr addrspace(1) %ptr, i64 42 syncscope("agent") seq_cst, align 8, !amdgpu.no.remote.memory !0
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @flat_atomic_max_ret_i32(ptr addrspace(1) %out, ptr %ptr) #1 {
|
|
; GFX9-LABEL: flat_atomic_max_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
|
|
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX9-NEXT: flat_atomic_smax v0, v[0:1], v2 glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: flat_atomic_max_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_add_u32 s12, s12, s17
|
|
; GFX10-NEXT: s_addc_u32 s13, s13, 0
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX10-NEXT: flat_atomic_smax v0, v[0:1], v2 glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: flat_atomic_max_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
|
; GFX11-NEXT: flat_atomic_max_i32 v0, v[0:1], v2 glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw max ptr %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @flat_atomic_max_ret_i64(ptr addrspace(1) %out, ptr %ptr) #1 {
|
|
; GFX9-LABEL: flat_atomic_max_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
|
|
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
|
; GFX9-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: flat_atomic_max_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_add_u32 s12, s12, s17
|
|
; GFX10-NEXT: s_addc_u32 s13, s13, 0
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX10-NEXT: v_mov_b32_e32 v3, s3
|
|
; GFX10-NEXT: flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: flat_atomic_max_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: flat_atomic_max_i64 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw max ptr %ptr, i64 42 syncscope("agent") seq_cst, align 8, !noalias.addrspace !1, !amdgpu.no.remote.memory !0
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @local_atomic_max_ret_i32(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
|
|
; GFX9-LABEL: local_atomic_max_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 42
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX9-NEXT: ds_max_rtn_i32 v0, v0, v1
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_max_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 42
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ds_max_rtn_i32 v0, v0, v1
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: local_atomic_max_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 42 :: v_dual_mov_b32 v0, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_max_rtn_i32 v0, v0, v1
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw max ptr addrspace(3) %ptr, i32 42 seq_cst, align 4
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @local_atomic_max_ret_i64(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
|
|
; GFX9-LABEL: local_atomic_max_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_max_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: local_atomic_max_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw max ptr addrspace(3) %ptr, i64 42 seq_cst, align 8
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
;===----------------------------------------------------------------------===;
|
|
; atomicrmw umin
|
|
;===----------------------------------------------------------------------===;
|
|
|
|
define amdgpu_kernel void @global_atomic_umin_ret_i32(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
|
|
; GFX9-LABEL: global_atomic_umin_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_atomic_umin v0, v1, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: global_atomic_umin_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_atomic_umin v0, v1, v0, s[2:3] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: global_atomic_umin_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_atomic_min_u32 v0, v1, v0, s[2:3] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umin ptr addrspace(1) %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @global_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
|
|
; GFX9-LABEL: global_atomic_umin_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_atomic_umin_x2 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: global_atomic_umin_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_atomic_umin_x2 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: global_atomic_umin_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_atomic_min_u64 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umin ptr addrspace(1) %ptr, i64 42 syncscope("agent") seq_cst, align 8, !amdgpu.no.remote.memory !0
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @flat_atomic_umin_ret_i32(ptr addrspace(1) %out, ptr %ptr) #1 {
|
|
; GFX9-LABEL: flat_atomic_umin_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
|
|
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX9-NEXT: flat_atomic_umin v0, v[0:1], v2 glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: flat_atomic_umin_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_add_u32 s12, s12, s17
|
|
; GFX10-NEXT: s_addc_u32 s13, s13, 0
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX10-NEXT: flat_atomic_umin v0, v[0:1], v2 glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: flat_atomic_umin_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
|
; GFX11-NEXT: flat_atomic_min_u32 v0, v[0:1], v2 glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umin ptr %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @flat_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr %ptr) #1 {
|
|
; GFX9-LABEL: flat_atomic_umin_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
|
|
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
|
; GFX9-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: flat_atomic_umin_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_add_u32 s12, s12, s17
|
|
; GFX10-NEXT: s_addc_u32 s13, s13, 0
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX10-NEXT: v_mov_b32_e32 v3, s3
|
|
; GFX10-NEXT: flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: flat_atomic_umin_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: flat_atomic_min_u64 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umin ptr %ptr, i64 42 syncscope("agent") seq_cst, align 8, !noalias.addrspace !1, !amdgpu.no.remote.memory !0
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @local_atomic_umin_ret_i32(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
|
|
; GFX9-LABEL: local_atomic_umin_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 42
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX9-NEXT: ds_min_rtn_u32 v0, v0, v1
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_umin_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 42
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ds_min_rtn_u32 v0, v0, v1
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: local_atomic_umin_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 42 :: v_dual_mov_b32 v0, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_min_rtn_u32 v0, v0, v1
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umin ptr addrspace(3) %ptr, i32 42 seq_cst, align 4
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @local_atomic_umin_ret_i64(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
|
|
; GFX9-LABEL: local_atomic_umin_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_umin_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: local_atomic_umin_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umin ptr addrspace(3) %ptr, i64 42 seq_cst, align 8
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
;===----------------------------------------------------------------------===;
|
|
; atomicrmw umax
|
|
;===----------------------------------------------------------------------===;
|
|
|
|
define amdgpu_kernel void @global_atomic_umax_ret_i32(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
|
|
; GFX9-LABEL: global_atomic_umax_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_atomic_umax v0, v1, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: global_atomic_umax_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_atomic_umax v0, v1, v0, s[2:3] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: global_atomic_umax_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_atomic_max_u32 v0, v1, v0, s[2:3] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umax ptr addrspace(1) %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @global_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #1 {
|
|
; GFX9-LABEL: global_atomic_umax_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_atomic_umax_x2 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: global_atomic_umax_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_atomic_umax_x2 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: global_atomic_umax_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_atomic_max_u64 v[0:1], v2, v[0:1], s[2:3] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umax ptr addrspace(1) %ptr, i64 42 syncscope("agent") seq_cst, align 8, !amdgpu.no.remote.memory !0
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @flat_atomic_umax_ret_i32(ptr addrspace(1) %out, ptr %ptr) #1 {
|
|
; GFX9-LABEL: flat_atomic_umax_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
|
|
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX9-NEXT: flat_atomic_umax v0, v[0:1], v2 glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: flat_atomic_umax_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_add_u32 s12, s12, s17
|
|
; GFX10-NEXT: s_addc_u32 s13, s13, 0
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, s3
|
|
; GFX10-NEXT: flat_atomic_umax v0, v[0:1], v2 glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: flat_atomic_umax_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 42
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
|
|
; GFX11-NEXT: flat_atomic_max_u32 v0, v[0:1], v2 glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umax ptr %ptr, i32 42 syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @flat_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr %ptr) #1 {
|
|
; GFX9-LABEL: flat_atomic_umax_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s12, s17
|
|
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s3
|
|
; GFX9-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_wbinvl1_vol
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: flat_atomic_umax_ret_i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_add_u32 s12, s12, s17
|
|
; GFX10-NEXT: s_addc_u32 s13, s13, 0
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
|
|
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX10-NEXT: v_mov_b32_e32 v3, s3
|
|
; GFX10-NEXT: flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl1_inv
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: flat_atomic_umax_ret_i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: flat_atomic_max_u64 v[0:1], v[2:3], v[0:1] glc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl1_inv
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umax ptr %ptr, i64 42 syncscope("agent") seq_cst, align 8, !noalias.addrspace !1, !amdgpu.no.remote.memory !0
|
|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @local_atomic_umax_ret_i32(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
|
|
; GFX9-LABEL: local_atomic_umax_ret_i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 42
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s2
|
|
; GFX9-NEXT: ds_max_rtn_u32 v0, v0, v1
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_umax_ret_i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 42
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: ds_max_rtn_u32 v0, v0, v1
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: buffer_gl0_inv
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: local_atomic_umax_ret_i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, 42 :: v_dual_mov_b32 v0, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_max_rtn_u32 v0, v0, v1
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umax ptr addrspace(3) %ptr, i32 42 seq_cst, align 4
|
|
store i32 %result, ptr addrspace(1) %out, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @local_atomic_umax_ret_i64(ptr addrspace(1) %out, ptr addrspace(3) %ptr) #1 {
|
|
; GFX9-LABEL: local_atomic_umax_ret_i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8
|
|
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 42
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s2
|
|
; GFX9-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: local_atomic_umax_ret_i64:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dword s0, s[8:9], 0x8
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; GFX10-NEXT: v_mov_b32_e32 v0, 42
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_mov_b32_e32 v2, s0
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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|
; GFX10-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
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|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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|
; GFX10-NEXT: buffer_gl0_inv
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|
; GFX10-NEXT: v_mov_b32_e32 v2, 0
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|
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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|
; GFX10-NEXT: s_endpgm
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|
;
|
|
; GFX11-LABEL: local_atomic_umax_ret_i64:
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|
; GFX11: ; %bb.0:
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|
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x8
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|
; GFX11-NEXT: v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
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|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, s0
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: buffer_gl0_inv
|
|
; GFX11-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
%result = atomicrmw umax ptr addrspace(3) %ptr, i64 42 seq_cst, align 8
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|
store i64 %result, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
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|
|
|
!0 = !{}
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|
!1 = !{i32 5, i32 6}
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GCN: {{.*}}
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