derek.holloway
7502bf64a4
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250 lines
9.9 KiB
LLVM
250 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
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define amdgpu_ps float @fpext_f16_to_f32_uniform(half inreg %a) {
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; GFX11-LABEL: fpext_f16_to_f32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fpext_f16_to_f32_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_cvt_f32_f16 s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: ; return to shader part epilog
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%result = fpext half %a to float
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ret float %result
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}
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define amdgpu_ps float @fpext_f16_to_f32_div(half %a) {
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; GFX11-FAKE16-LABEL: fpext_f16_to_f32_div:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX11-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX11-TRUE16-LABEL: fpext_f16_to_f32_div:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX12-FAKE16-LABEL: fpext_f16_to_f32_div:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX12-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX12-TRUE16-LABEL: fpext_f16_to_f32_div:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
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; GFX12-TRUE16-NEXT: ; return to shader part epilog
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%result = fpext half %a to float
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ret float %result
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}
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define amdgpu_ps void @fpext_f32_to_f64_uniform(float inreg %a, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fpext_f32_to_f64_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
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; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: fpext_f32_to_f64_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
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; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX12-NEXT: s_endpgm
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%result = fpext float %a to double
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store double %result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @fpext_f32_to_f64_div(float %a, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fpext_f32_to_f64_div:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
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; GFX11-NEXT: global_store_b64 v[1:2], v[3:4], off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: fpext_f32_to_f64_div:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
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; GFX12-NEXT: global_store_b64 v[1:2], v[3:4], off
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; GFX12-NEXT: s_endpgm
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%result = fpext float %a to double
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store double %result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @fpext_f16_to_f64_uniform(half inreg %a, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fpext_f16_to_f64_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
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; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: fpext_f16_to_f64_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_cvt_f32_f16 s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
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; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
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; GFX12-NEXT: s_endpgm
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%result = fpext half %a to double
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store double %result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @fpext_f16_to_f64_div(half %a, ptr addrspace(1) %ptr) {
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; GFX11-FAKE16-LABEL: fpext_f16_to_f64_div:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
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; GFX11-FAKE16-NEXT: global_store_b64 v[1:2], v[3:4], off
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; GFX11-FAKE16-NEXT: s_endpgm
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;
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; GFX11-TRUE16-LABEL: fpext_f16_to_f64_div:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
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; GFX11-TRUE16-NEXT: global_store_b64 v[1:2], v[3:4], off
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; GFX11-TRUE16-NEXT: s_endpgm
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;
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; GFX12-FAKE16-LABEL: fpext_f16_to_f64_div:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-FAKE16-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
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; GFX12-FAKE16-NEXT: global_store_b64 v[1:2], v[3:4], off
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; GFX12-FAKE16-NEXT: s_endpgm
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;
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; GFX12-TRUE16-LABEL: fpext_f16_to_f64_div:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-TRUE16-NEXT: v_cvt_f64_f32_e32 v[3:4], v0
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; GFX12-TRUE16-NEXT: global_store_b64 v[1:2], v[3:4], off
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; GFX12-TRUE16-NEXT: s_endpgm
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%result = fpext half %a to double
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store double %result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps <2 x float> @fpext_v2f16_to_v2f32_uniform(<2 x half> inreg %a) {
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; GFX11-LABEL: fpext_v2f16_to_v2f32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_lshr_b32 s1, s0, 16
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; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0
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; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s1
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fpext_v2f16_to_v2f32_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_cvt_f32_f16 s1, s0
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; GFX12-NEXT: s_cvt_hi_f32_f16 s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
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; GFX12-NEXT: ; return to shader part epilog
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%result = fpext <2 x half> %a to <2 x float>
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ret <2 x float> %result
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}
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define amdgpu_ps <2 x float> @fpext_v2f16_to_v2f32_div(<2 x half> %a) {
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; GFX11-FAKE16-LABEL: fpext_v2f16_to_v2f32_div:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
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; GFX11-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX11-TRUE16-LABEL: fpext_v2f16_to_v2f32_div:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
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; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.h
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX12-FAKE16-LABEL: fpext_v2f16_to_v2f32_div:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
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; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
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; GFX12-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX12-TRUE16-LABEL: fpext_v2f16_to_v2f32_div:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v0.l
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; GFX12-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.h
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX12-TRUE16-NEXT: ; return to shader part epilog
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%result = fpext <2 x half> %a to <2 x float>
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ret <2 x float> %result
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}
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define amdgpu_ps void @fpext_v2f32_to_v2f64_uniform(<2 x float> inreg %a, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fpext_v2f32_to_v2f64_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[4:5], s1
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_readfirstlane_b32 s3, v5
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; GFX11-NEXT: v_readfirstlane_b32 s0, v2
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
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; GFX11-NEXT: v_readfirstlane_b32 s1, v3
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; GFX11-NEXT: v_readfirstlane_b32 s2, v4
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; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
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; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: fpext_v2f32_to_v2f64_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[4:5], s1
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX12-NEXT: v_readfirstlane_b32 s3, v5
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; GFX12-NEXT: v_readfirstlane_b32 s0, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
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; GFX12-NEXT: v_readfirstlane_b32 s1, v3
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; GFX12-NEXT: v_readfirstlane_b32 s2, v4
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; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
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; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2
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; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off
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; GFX12-NEXT: s_endpgm
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%result = fpext <2 x float> %a to <2 x double>
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store <2 x double> %result, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @fpext_v2f32_to_v2f64_div(<2 x float> %a, ptr addrspace(1) %ptr) {
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; GFX11-LABEL: fpext_v2f32_to_v2f64_div:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[4:5], v0
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; GFX11-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
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; GFX11-NEXT: global_store_b128 v[2:3], v[4:7], off
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: fpext_v2f32_to_v2f64_div:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[4:5], v0
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; GFX12-NEXT: v_cvt_f64_f32_e32 v[6:7], v1
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; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off
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; GFX12-NEXT: s_endpgm
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%result = fpext <2 x float> %a to <2 x double>
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store <2 x double> %result, ptr addrspace(1) %ptr
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ret void
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}
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