derek.holloway
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52 lines
2.2 KiB
LLVM
52 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-s-branch-bits=4 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
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; Make sure the inst size estimate for D16 pseudo insts are not 0
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define amdgpu_kernel void @long_forward_branch_gfx11plus(ptr addrspace(1) %in, ptr addrspace(1) %out, i32 %cnd) #0 {
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; GFX11-LABEL: long_forward_branch_gfx11plus:
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; GFX11: ; %bb.0: ; %bb0
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; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x34
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_cmp_eq_u32 s0, 0
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; GFX11-NEXT: s_cbranch_scc0 .LBB0_1
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; GFX11-NEXT: ; %bb.3: ; %bb0
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; GFX11-NEXT: s_getpc_b64 s[6:7]
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; GFX11-NEXT: .Lpost_getpc0:
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; GFX11-NEXT: s_add_u32 s6, s6, (.LBB0_2-.Lpost_getpc0)&4294967295
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; GFX11-NEXT: s_addc_u32 s7, s7, (.LBB0_2-.Lpost_getpc0)>>32
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; GFX11-NEXT: s_setpc_b64 s[6:7]
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; GFX11-NEXT: .LBB0_1: ; %bb2
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1]
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; GFX11-NEXT: global_load_d16_hi_b16 v0, v1, s[0:1] offset:2
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; GFX11-NEXT: s_waitcnt vmcnt(1)
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; GFX11-NEXT: global_store_b16 v1, v0, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: global_store_d16_hi_b16 v1, v0, s[2:3] offset:2
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; GFX11-NEXT: .LBB0_2: ; %bb3
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; GFX11-NEXT: s_endpgm
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bb0:
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;%idx = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr inbounds i16, ptr addrspace(1) %in, i32 0
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%gep1 = getelementptr inbounds i16, ptr addrspace(1) %in, i32 1
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%out0 = getelementptr inbounds i16, ptr addrspace(1) %out, i32 0
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%out1 = getelementptr inbounds i16, ptr addrspace(1) %out, i32 1
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%cmp = icmp eq i32 %cnd, 0
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br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
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bb2:
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; Estimated as 32-bytes on gfx11 (requiring a long branch)
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%load0 = load i16, ptr addrspace(1) %gep0
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%load1 = load i16, ptr addrspace(1) %gep1
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store i16 %load0, ptr addrspace(1) %out0
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store i16 %load1, ptr addrspace(1) %out1
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br label %bb3
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bb3:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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