derek.holloway
7502bf64a4
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219 lines
8.2 KiB
LLVM
219 lines
8.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s -check-prefix=GISEL
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; Check for optimizing the passed implicit workitem ID based on the
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; required group size. This should avoid a few bit packing operations.
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declare hidden void @callee() #0
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define amdgpu_kernel void @known_x_0(ptr addrspace(1) %out) !reqd_work_group_size !0 {
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; CHECK-LABEL: known_x_0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: v_lshlrev_b32_e32 v0, 20, v2
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; CHECK-NEXT: v_lshl_or_b32 v31, v1, 10, v0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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;
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; GISEL-LABEL: known_x_0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GISEL-NEXT: s_add_u32 s0, s0, s17
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; GISEL-NEXT: s_addc_u32 s1, s1, 0
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; GISEL-NEXT: v_lshlrev_b32_e32 v0, 20, v2
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; GISEL-NEXT: v_lshl_or_b32 v31, v1, 10, v0
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; GISEL-NEXT: s_getpc_b64 s[4:5]
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; GISEL-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; GISEL-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; GISEL-NEXT: s_mov_b32 s32, 0
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; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GISEL-NEXT: s_endpgm
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call void @callee()
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ret void
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}
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; CHECK: .amdhsa_system_vgpr_workitem_id 2
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define amdgpu_kernel void @known_y_0(ptr addrspace(1) %out) !reqd_work_group_size !1 {
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; CHECK-LABEL: known_y_0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; CHECK-NEXT: v_lshl_or_b32 v31, v2, 20, v0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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;
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; GISEL-LABEL: known_y_0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GISEL-NEXT: s_add_u32 s0, s0, s17
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; GISEL-NEXT: s_addc_u32 s1, s1, 0
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; GISEL-NEXT: v_lshl_or_b32 v31, v2, 20, v0
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; GISEL-NEXT: s_getpc_b64 s[4:5]
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; GISEL-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; GISEL-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; GISEL-NEXT: s_mov_b32 s32, 0
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; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GISEL-NEXT: s_endpgm
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call void @callee()
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ret void
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}
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; CHECK: .amdhsa_system_vgpr_workitem_id 2
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define amdgpu_kernel void @known_z_0(ptr addrspace(1) %out) !reqd_work_group_size !2 {
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; CHECK-LABEL: known_z_0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; CHECK-NEXT: v_lshl_or_b32 v31, v1, 10, v0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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;
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; GISEL-LABEL: known_z_0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GISEL-NEXT: s_add_u32 s0, s0, s17
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; GISEL-NEXT: s_addc_u32 s1, s1, 0
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; GISEL-NEXT: v_lshl_or_b32 v31, v1, 10, v0
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; GISEL-NEXT: s_getpc_b64 s[4:5]
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; GISEL-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; GISEL-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; GISEL-NEXT: s_mov_b32 s32, 0
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; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GISEL-NEXT: s_endpgm
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call void @callee()
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ret void
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}
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; CHECK: .amdhsa_system_vgpr_workitem_id 1
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define amdgpu_kernel void @known_yz_0(ptr addrspace(1) %out) !reqd_work_group_size !3 {
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; CHECK-LABEL: known_yz_0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; CHECK-NEXT: v_mov_b32_e32 v31, v0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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;
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; GISEL-LABEL: known_yz_0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GISEL-NEXT: s_add_u32 s0, s0, s17
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; GISEL-NEXT: s_addc_u32 s1, s1, 0
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; GISEL-NEXT: s_getpc_b64 s[4:5]
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; GISEL-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; GISEL-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; GISEL-NEXT: v_mov_b32_e32 v31, v0
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; GISEL-NEXT: s_mov_b32 s32, 0
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; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GISEL-NEXT: s_endpgm
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call void @callee()
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ret void
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}
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; CHECK: .amdhsa_system_vgpr_workitem_id 0
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define amdgpu_kernel void @known_xz_0(ptr addrspace(1) %out) !reqd_work_group_size !4 {
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; CHECK-LABEL: known_xz_0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; CHECK-NEXT: v_lshlrev_b32_e32 v31, 10, v1
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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;
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; GISEL-LABEL: known_xz_0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GISEL-NEXT: s_add_u32 s0, s0, s17
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; GISEL-NEXT: s_addc_u32 s1, s1, 0
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; GISEL-NEXT: v_lshlrev_b32_e32 v31, 10, v1
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; GISEL-NEXT: s_getpc_b64 s[4:5]
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; GISEL-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; GISEL-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; GISEL-NEXT: s_mov_b32 s32, 0
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; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GISEL-NEXT: s_endpgm
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call void @callee()
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ret void
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}
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; CHECK: .amdhsa_system_vgpr_workitem_id 1
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define amdgpu_kernel void @known_xyz_0(ptr addrspace(1) %out) !reqd_work_group_size !5 {
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; CHECK-LABEL: known_xyz_0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s17
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; CHECK-NEXT: v_mov_b32_e32 v31, 0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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;
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; GISEL-LABEL: known_xyz_0:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_add_u32 flat_scratch_lo, s12, s17
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; GISEL-NEXT: s_addc_u32 flat_scratch_hi, s13, 0
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; GISEL-NEXT: s_add_u32 s0, s0, s17
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; GISEL-NEXT: s_addc_u32 s1, s1, 0
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; GISEL-NEXT: s_getpc_b64 s[4:5]
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; GISEL-NEXT: s_add_u32 s4, s4, callee@rel32@lo+4
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; GISEL-NEXT: s_addc_u32 s5, s5, callee@rel32@hi+12
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; GISEL-NEXT: v_mov_b32_e32 v31, 0
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; GISEL-NEXT: s_mov_b32 s32, 0
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; GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GISEL-NEXT: s_endpgm
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call void @callee()
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ret void
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}
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; CHECK: .amdhsa_system_vgpr_workitem_id 0
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attributes #0 = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" }
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!0 = !{i32 1, i32 64, i32 64}
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!1 = !{i32 64, i32 1, i32 64}
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!2 = !{i32 64, i32 64, i32 1}
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!3 = !{i32 64, i32 1, i32 1}
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!4 = !{i32 1, i32 64, i32 1}
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!5 = !{i32 1, i32 1, i32 1}
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