TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s

# Initially %2 starts out with 2 subranges (one for sub0, and one for
# the rest of the lanes). After %2 is split, after refineSubRanges the
# newly created register has a different set of lane masks since the
# copy bundle uses 2 different defs to cover the register. This was
# fixed by doing refineSubRanges after all the COPYs being inserted.

---
name: subrange_for_this_mask_not_found
tracksRegLiveness: true
machineFunctionInfo:
  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
  stackPtrOffsetReg: '$sgpr32'
  occupancy:       7
body:             |
  ; CHECK-LABEL: name: subrange_for_this_mask_not_found
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   dead [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]
  ; CHECK-NEXT:   S_NOP 0, implicit [[DEF1]]
  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   undef [[COPY1:%[0-9]+]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {
  ; CHECK-NEXT:     internal [[COPY1]].sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16:av_1024_align2 = COPY [[COPY]].sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16
  ; CHECK-NEXT:     internal [[COPY1]].sub17_sub18_sub19:av_1024_align2 = COPY [[COPY]].sub17_sub18_sub19
  ; CHECK-NEXT:   }
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]].sub0:av_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   S_NOP 0, implicit [[COPY1]].sub0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_NOP 0, implicit [[COPY1]]
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.4:
  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.5(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
  ; CHECK-NEXT:   S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.5:
  ; CHECK-NEXT:   undef [[COPY2:%[0-9]+]].sub0:vreg_1024_align2 = COPY [[DEF]]
  ; CHECK-NEXT:   S_NOP 0, implicit [[COPY2]]
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:vreg_1024_align2 = IMPLICIT_DEF
    %2:vreg_1024_align2 = COPY %1

  bb.1:
    %5:vreg_64 = IMPLICIT_DEF
    S_NOP 0, implicit %1
    S_NOP 0, implicit %1
    %1:vreg_1024_align2 = IMPLICIT_DEF
    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc

  bb.3:
    %2.sub0:vreg_1024_align2 = IMPLICIT_DEF
    S_NOP 0, implicit %2.sub0

  bb.4:
    S_NOP 0, implicit %2

  bb.5:
    %2:vreg_1024_align2 = IMPLICIT_DEF
    S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc

  bb.6:
    undef %4.sub0:vreg_1024_align2 = COPY %0
    S_NOP 0, implicit %4
...