derek.holloway
7502bf64a4
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39 lines
1.1 KiB
LLVM
39 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
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; CHECK: {{^}}fcmp_sext:
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; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define amdgpu_kernel void @fcmp_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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entry:
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%0 = load float, ptr addrspace(1) %in
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%arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %in, i32 1
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%1 = load float, ptr addrspace(1) %arrayidx1
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%cmp = fcmp oeq float %0, %1
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%sext = sext i1 %cmp to i32
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store i32 %sext, ptr addrspace(1) %out
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ret void
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}
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; This test checks that a setcc node with f32 operands is lowered to a
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; SET*_DX10 instruction. Previously we were lowering this to:
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; SET* + FP_TO_SINT
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; CHECK: {{^}}fcmp_br:
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; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
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; CHECK-NEXT: {{[0-9]+\(5.0}}
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define amdgpu_kernel void @fcmp_br(ptr addrspace(1) %out, float %in) {
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entry:
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%0 = fcmp oeq float %in, 5.0
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br i1 %0, label %IF, label %ENDIF
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IF:
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%1 = getelementptr i32, ptr addrspace(1) %out, i32 1
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store i32 0, ptr addrspace(1) %1
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br label %ENDIF
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ENDIF:
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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