derek.holloway
7502bf64a4
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80 lines
3.3 KiB
LLVM
80 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck %s
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define protected amdgpu_kernel void @IllegalGEPConst(i32 %a, ptr addrspace(1) %b, double %c) {
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; CHECK-LABEL: IllegalGEPConst:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
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; CHECK-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
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; CHECK-NEXT: s_load_dword s8, s[4:5], 0x24
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
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; CHECK-NEXT: s_mov_b32 s14, -1
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; CHECK-NEXT: s_mov_b32 s15, 0xe00000
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; CHECK-NEXT: s_add_u32 s12, s12, s11
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; CHECK-NEXT: s_addc_u32 s13, s13, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_ashr_i32 s9, s8, 31
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; CHECK-NEXT: s_lshl_b64 s[4:5], s[8:9], 3
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; CHECK-NEXT: s_add_u32 s0, s0, s4
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; CHECK-NEXT: s_addc_u32 s1, s1, s5
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; CHECK-NEXT: s_add_u32 s0, s0, -8
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; CHECK-NEXT: s_mov_b64 s[6:7], src_shared_base
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; CHECK-NEXT: s_addc_u32 s1, s1, -1
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; CHECK-NEXT: s_cmp_eq_u32 s1, s7
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; CHECK-NEXT: s_cselect_b64 s[4:5], -1, 0
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; CHECK-NEXT: s_andn2_b64 vcc, exec, s[4:5]
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; CHECK-NEXT: s_mov_b64 s[4:5], -1
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; CHECK-NEXT: s_cbranch_vccnz .LBB0_3
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; CHECK-NEXT: ; %bb.1: ; %Flow6
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; CHECK-NEXT: s_andn2_b64 vcc, exec, s[4:5]
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; CHECK-NEXT: s_cbranch_vccz .LBB0_8
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; CHECK-NEXT: .LBB0_2: ; %atomicrmw.phi
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: .LBB0_3: ; %atomicrmw.check.private
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; CHECK-NEXT: s_mov_b64 s[4:5], src_private_base
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; CHECK-NEXT: s_cmp_eq_u32 s1, s5
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; CHECK-NEXT: s_cselect_b64 s[4:5], -1, 0
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; CHECK-NEXT: s_andn2_b64 vcc, exec, s[4:5]
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; CHECK-NEXT: s_mov_b64 s[4:5], -1
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; CHECK-NEXT: s_cbranch_vccz .LBB0_5
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; CHECK-NEXT: ; %bb.4: ; %atomicrmw.global
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; CHECK-NEXT: global_atomic_add_f64 v0, v[2:3], s[0:1]
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_wbinvl1_vol
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; CHECK-NEXT: s_mov_b64 s[4:5], 0
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; CHECK-NEXT: .LBB0_5: ; %Flow
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; CHECK-NEXT: s_andn2_b64 vcc, exec, s[4:5]
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; CHECK-NEXT: s_cbranch_vccnz .LBB0_7
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; CHECK-NEXT: ; %bb.6: ; %atomicrmw.private
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; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
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; CHECK-NEXT: s_cselect_b32 s4, s0, -1
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; CHECK-NEXT: v_mov_b32_e32 v2, s4
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; CHECK-NEXT: buffer_load_dword v0, v2, s[12:15], 0 offen
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; CHECK-NEXT: buffer_load_dword v1, v2, s[12:15], 0 offen offset:4
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
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; CHECK-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
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; CHECK-NEXT: buffer_store_dword v1, v2, s[12:15], 0 offen offset:4
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; CHECK-NEXT: .LBB0_7: ; %Flow5
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; CHECK-NEXT: s_cbranch_execnz .LBB0_2
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; CHECK-NEXT: .LBB0_8: ; %atomicrmw.shared
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; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
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; CHECK-NEXT: s_cselect_b32 s0, s0, -1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; CHECK-NEXT: ds_add_f64 v0, v[2:3]
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_endpgm
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entry:
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%i = add nsw i32 %a, -1
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%i.2 = sext i32 %i to i64
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%i.3 = getelementptr inbounds double, ptr addrspace(1) %b, i64 %i.2
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%i.4 = addrspacecast ptr addrspace(1) %i.3 to ptr
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%i.5 = atomicrmw fadd ptr %i.4, double %c syncscope("agent") seq_cst, align 8, !amdgpu.no.fine.grained.memory !0
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ret void
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}
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!0 = !{}
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