derek.holloway
7502bf64a4
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550 lines
19 KiB
YAML
550 lines
19 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: ds_atomic_async_barrier_arrive_b64
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: ds_atomic_async_barrier_arrive_b64
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: S_WAITCNT_DEPCTR .VmVsrc_0
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; GCN-NEXT: DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 $vgpr1, 0, 0, implicit-def $asynccnt, implicit $asynccnt, implicit $exec
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; GCN-NEXT: S_WAITCNT_DEPCTR .VmVsrc_0
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DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 $vgpr1, 0, 0, implicit-def $asynccnt, implicit $asynccnt, implicit $exec
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...
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---
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name: write_s102_read_flat_scr_base_lo
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s102_read_flat_scr_base_lo
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr102 = S_MOV_B32 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
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$sgpr102 = S_MOV_B32 0
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$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
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...
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---
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name: write_s103_read_flat_scr_base_hi
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s103_read_flat_scr_base_hi
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr103 = S_MOV_B32 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
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$sgpr103 = S_MOV_B32 0
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$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
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...
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---
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name: write_s102_read_flat_scr_base
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: write_s102_read_flat_scr_base
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; GCN: $sgpr102 = S_MOV_B32 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
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$sgpr102 = S_MOV_B32 0
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$sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
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...
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---
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name: write_s103_read_flat_scr_base
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: write_s103_read_flat_scr_base
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; GCN: $sgpr103 = S_MOV_B32 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
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$sgpr103 = S_MOV_B32 0
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$sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
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...
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---
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name: write_s102_s103_read_flat_scr_base
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: write_s102_s103_read_flat_scr_base
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; GCN: $sgpr102_sgpr103 = S_MOV_B64 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
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$sgpr102_sgpr103 = S_MOV_B64 0
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$sgpr0_sgpr1 = S_MOV_B64 $src_flat_scratch_base
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...
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---
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name: write_s102_getreg_flat_scr_base_lo
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s102_getreg_flat_scr_base_lo
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr102 = S_MOV_B32 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $sgpr1 = S_GETREG_B32 20, implicit $mode
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$sgpr102 = S_MOV_B32 0
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$sgpr1 = S_GETREG_B32 20, implicit $mode
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...
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---
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name: write_s103_getreg_flat_scr_base_hi
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s103_getreg_flat_scr_base_hi
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr103 = S_MOV_B32 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $sgpr1 = S_GETREG_B32 21, implicit $mode
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$sgpr103 = S_MOV_B32 0
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$sgpr1 = S_GETREG_B32 21, implicit $mode
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...
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---
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name: write_s102_s103_getreg_flat_scr_base_hi
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: write_s102_s103_getreg_flat_scr_base_hi
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; GCN: $sgpr102_sgpr103 = S_MOV_B64 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $sgpr1 = S_GETREG_B32 21, implicit $mode
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$sgpr102_sgpr103 = S_MOV_B64 0
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$sgpr1 = S_GETREG_B32 21, implicit $mode
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...
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---
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name: write_s102_read_flat_scr_base_lo_9_salu_valu
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_9_salu_valu
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr102 = S_MOV_B32 0
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; GCN-NEXT: $sgpr0 = S_MOV_B32 0
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; GCN-NEXT: $sgpr1 = S_MOV_B32 0
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; GCN-NEXT: $sgpr2_sgpr3 = S_MOV_B64 0
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; GCN-NEXT: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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; GCN-NEXT: $vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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; GCN-NEXT: $sgpr4 = S_MOV_B32 0
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; GCN-NEXT: $sgpr5 = S_MOV_B32 0
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; GCN-NEXT: $sgpr6 = S_MOV_B32 0
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; GCN-NEXT: $sgpr7 = S_MOV_B32 0
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; GCN-NEXT: $sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
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$sgpr102 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr1 = S_MOV_B32 0
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$sgpr2_sgpr3 = S_MOV_B64 0
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$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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$vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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; NOP does not count because it does not write SGPRs
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S_NOP 0
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; DS_READ_B32 does not count because it is not SALU or VALU
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$vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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$sgpr4 = S_MOV_B32 0
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$sgpr5 = S_MOV_B32 0
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$sgpr6 = S_MOV_B32 0
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$sgpr7 = S_MOV_B32 0
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; S_LOAD_DWORDX2_IMM does not count because it is not SALU
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$sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
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...
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---
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name: write_s102_read_flat_scr_base_lo_10_salu_valu_expired
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_10_salu_valu_expired
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr102 = S_MOV_B32 0
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; GCN-NEXT: $sgpr0 = S_MOV_B32 0
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; GCN-NEXT: $sgpr1 = S_MOV_B32 0
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; GCN-NEXT: $sgpr2_sgpr3 = S_MOV_B64 0
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; GCN-NEXT: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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; GCN-NEXT: $vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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; GCN-NEXT: $sgpr4 = S_MOV_B32 0
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; GCN-NEXT: $sgpr5 = S_MOV_B32 0
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; GCN-NEXT: $sgpr6 = S_MOV_B32 0
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; GCN-NEXT: $sgpr7 = S_MOV_B32 0
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; GCN-NEXT: $sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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; GCN-NEXT: $sgpr10 = S_MOV_B32 0
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; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
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$sgpr102 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr1 = S_MOV_B32 0
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$sgpr2_sgpr3 = S_MOV_B64 0
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$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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$vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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; NOP does not count because it does not write SGPRs
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S_NOP 0
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; DS_READ_B32 does not count because it is not SALU or VALU
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$vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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$sgpr4 = S_MOV_B32 0
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$sgpr5 = S_MOV_B32 0
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$sgpr6 = S_MOV_B32 0
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$sgpr7 = S_MOV_B32 0
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; S_LOAD_DWORDX2_IMM does not count because it is not SALU
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$sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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$sgpr10 = S_MOV_B32 0
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$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
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...
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---
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name: write_s103_read_flat_scr_base_hi_9_salu_valu
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s103_read_flat_scr_base_hi_9_salu_valu
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr103 = S_MOV_B32 0
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; GCN-NEXT: $sgpr0 = S_MOV_B32 0
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; GCN-NEXT: $sgpr1 = S_MOV_B32 0
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; GCN-NEXT: $sgpr2_sgpr3 = S_MOV_B64 0
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; GCN-NEXT: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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; GCN-NEXT: $vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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; GCN-NEXT: $sgpr4 = S_MOV_B32 0
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; GCN-NEXT: $sgpr5 = S_MOV_B32 0
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; GCN-NEXT: $sgpr6 = S_MOV_B32 0
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; GCN-NEXT: $sgpr7 = S_MOV_B32 0
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; GCN-NEXT: $sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
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; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
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$sgpr103 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr1 = S_MOV_B32 0
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$sgpr2_sgpr3 = S_MOV_B64 0
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$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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$vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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; NOP does not count because it does not write SGPRs
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S_NOP 0
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; DS_READ_B32 does not count because it is not SALU or VALU
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$vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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$sgpr4 = S_MOV_B32 0
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$sgpr5 = S_MOV_B32 0
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$sgpr6 = S_MOV_B32 0
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$sgpr7 = S_MOV_B32 0
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; S_LOAD_DWORDX2_IMM does not count because it is not SALU
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$sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
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...
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---
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name: write_s103_read_flat_scr_base_hi_10_salu_valu_expired
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: write_s103_read_flat_scr_base_hi_10_salu_valu_expired
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: $sgpr103 = S_MOV_B32 0
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; GCN-NEXT: $sgpr0 = S_MOV_B32 0
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; GCN-NEXT: $sgpr1 = S_MOV_B32 0
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; GCN-NEXT: $sgpr2_sgpr3 = S_MOV_B64 0
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; GCN-NEXT: $vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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; GCN-NEXT: $vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec
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; GCN-NEXT: S_NOP 0
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; GCN-NEXT: $vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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; GCN-NEXT: $sgpr4 = S_MOV_B32 0
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; GCN-NEXT: $sgpr5 = S_MOV_B32 0
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; GCN-NEXT: $sgpr6 = S_MOV_B32 0
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; GCN-NEXT: $sgpr7 = S_MOV_B32 0
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; GCN-NEXT: $sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
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; GCN-NEXT: $sgpr10 = S_MOV_B32 0
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; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
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$sgpr103 = S_MOV_B32 0
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$sgpr0 = S_MOV_B32 0
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$sgpr1 = S_MOV_B32 0
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$sgpr2_sgpr3 = S_MOV_B64 0
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$vgpr1, $vcc_lo = V_ADDC_U32_e64 0, $vgpr0, $sgpr0, 0, implicit $exec
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$vgpr2 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
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; NOP does not count because it does not write SGPRs
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S_NOP 0
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; DS_READ_B32 does not count because it is not SALU or VALU
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$vgpr3 = DS_READ_B32 $vgpr0, 0, 0, implicit $m0, implicit $exec
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$sgpr4 = S_MOV_B32 0
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$sgpr5 = S_MOV_B32 0
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$sgpr6 = S_MOV_B32 0
|
|
$sgpr7 = S_MOV_B32 0
|
|
; S_LOAD_DWORDX2_IMM does not count because it is not SALU
|
|
$sgpr8_sgpr9 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0
|
|
$sgpr10 = S_MOV_B32 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_read_flat_scr_base_hi_no_hazard
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: write_s102_read_flat_scr_base_hi_no_hazard
|
|
; GCN: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
|
|
$sgpr102 = S_MOV_B32 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_read_flat_scr_base_lo_expired_by_wait0
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_expired_by_wait0
|
|
; GCN: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaVdst_0_VaSdst_0_VaSsrc_0_HoldCnt_0_VmVsrc_0_VaVcc_0_SaSdst_0
|
|
; GCN-NEXT: S_NOP 0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
$sgpr102 = S_MOV_B32 0
|
|
S_WAITCNT_DEPCTR 0
|
|
S_NOP 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_read_flat_scr_base_lo_expired_by_wait_vs_sdst_sa_sdst
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_expired_by_wait_vs_sdst_sa_sdst
|
|
; GCN: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
|
|
; GCN-NEXT: S_NOP 0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
$sgpr102 = S_MOV_B32 0
|
|
S_WAITCNT_DEPCTR 61950
|
|
S_NOP 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_read_flat_scr_base_lo_not_expired_by_wait_va_sdst_only
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_not_expired_by_wait_va_sdst_only
|
|
; GCN: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0
|
|
; GCN-NEXT: S_NOP 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
$sgpr102 = S_MOV_B32 0
|
|
S_WAITCNT_DEPCTR 61951
|
|
S_NOP 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_read_flat_scr_base_lo_not_expired_by_wait_sa_sdst_only
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_not_expired_by_wait_sa_sdst_only
|
|
; GCN: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .SaSdst_0
|
|
; GCN-NEXT: S_NOP 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
$sgpr102 = S_MOV_B32 0
|
|
S_WAITCNT_DEPCTR 65534
|
|
S_NOP 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_write_s103_read_flat_scr_base_lo_read_flat_scr_base_hi
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
; GCN-LABEL: name: write_s102_write_s103_read_flat_scr_base_lo_read_flat_scr_base_hi
|
|
; GCN: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr103 = S_MOV_B32 0
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
; GCN-NEXT: $vgpr1 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
|
|
$sgpr102 = S_MOV_B32 0
|
|
$sgpr103 = S_MOV_B32 0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
$vgpr1 = V_ADD_U32_e32 $src_flat_scratch_base_hi, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: write_s102_read_flat_scr_base_lo_cross_blocks
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; GCN-LABEL: name: write_s102_read_flat_scr_base_lo_cross_blocks
|
|
; GCN: bb.0:
|
|
; GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; GCN-NEXT: liveins: $vgpr0, $sgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
|
|
; GCN-NEXT: $sgpr1 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr2 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr3 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr4 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr5 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr6 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr7 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr8 = S_MOV_B32 0
|
|
; GCN-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc
|
|
; GCN-NEXT: S_BRANCH %bb.1
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: bb.1:
|
|
; GCN-NEXT: successors: %bb.2(0x80000000)
|
|
; GCN-NEXT: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: $sgpr102 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr1 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr2 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr3 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr4 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr5 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr6 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr7 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr8 = S_MOV_B32 0
|
|
; GCN-NEXT: $sgpr9 = S_MOV_B32 0
|
|
; GCN-NEXT: S_BRANCH %bb.2
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: bb.2:
|
|
; GCN-NEXT: liveins: $vgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: S_WAITCNT_DEPCTR .VaSdst_0_SaSdst_0
|
|
; GCN-NEXT: $vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
bb.0:
|
|
liveins: $vgpr0, $sgpr0
|
|
$sgpr102 = S_ADD_U32 $sgpr0, 0, implicit-def $scc
|
|
$sgpr1 = S_MOV_B32 0
|
|
$sgpr2 = S_MOV_B32 0
|
|
$sgpr3 = S_MOV_B32 0
|
|
$sgpr4 = S_MOV_B32 0
|
|
$sgpr5 = S_MOV_B32 0
|
|
$sgpr6 = S_MOV_B32 0
|
|
$sgpr7 = S_MOV_B32 0
|
|
$sgpr8 = S_MOV_B32 0
|
|
S_CBRANCH_SCC0 %bb.2, implicit $scc
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
liveins: $vgpr0
|
|
$sgpr102 = S_MOV_B32 0
|
|
$sgpr1 = S_MOV_B32 0
|
|
$sgpr2 = S_MOV_B32 0
|
|
$sgpr3 = S_MOV_B32 0
|
|
$sgpr4 = S_MOV_B32 0
|
|
$sgpr5 = S_MOV_B32 0
|
|
$sgpr6 = S_MOV_B32 0
|
|
$sgpr7 = S_MOV_B32 0
|
|
$sgpr8 = S_MOV_B32 0
|
|
$sgpr9 = S_MOV_B32 0
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
liveins: $vgpr0
|
|
$vgpr0 = V_ADD_U32_e32 $src_flat_scratch_base_lo, $vgpr0, implicit $exec
|
|
...
|
|
|
|
---
|
|
name: s_setreg_b32_hwreg_mode
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
; GCN-LABEL: name: s_setreg_b32_hwreg_mode
|
|
; GCN: liveins: $sgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode
|
|
S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode
|
|
...
|
|
|
|
---
|
|
name: s_setreg_b32_mode
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
; GCN-LABEL: name: s_setreg_b32_mode
|
|
; GCN: liveins: $sgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: S_SETREG_B32_mode $sgpr0, 1, implicit-def $mode, implicit $mode
|
|
S_SETREG_B32_mode $sgpr0, 1, implicit-def $mode, implicit $mode
|
|
...
|
|
|
|
---
|
|
name: s_setreg_imm32_b32_hwreg_mode
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
; GCN-LABEL: name: s_setreg_imm32_b32_hwreg_mode
|
|
; GCN: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: S_SETREG_IMM32_B32 1, 1, implicit-def $mode, implicit $mode
|
|
S_SETREG_IMM32_B32 1, 1, implicit-def $mode, implicit $mode
|
|
...
|
|
|
|
---
|
|
name: s_setreg_imm32_b32_mode
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
; GCN-LABEL: name: s_setreg_imm32_b32_mode
|
|
; GCN: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: V_NOP_e32 implicit $exec
|
|
; GCN-NEXT: S_SETREG_IMM32_B32_mode 1, 1, implicit-def $mode, implicit $mode
|
|
S_SETREG_IMM32_B32_mode 1, 1, implicit-def $mode, implicit $mode
|
|
...
|