derek.holloway
7502bf64a4
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306 lines
17 KiB
YAML
306 lines
17 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=DEFAULT %s
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--- |
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define void @tensor_load_tensor_load() #0 { ret void }
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define void @tensor_wait_tensor_load() #0 { ret void }
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define void @tensor_wait_tensor_wait() #0 { ret void }
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define void @tensor_load_tensor_wait() #0 { ret void }
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define void @async_load_async_load() #0 { ret void }
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define void @async_wait_async_load() #0 { ret void }
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define void @async_wait_async_wait() #0 { ret void }
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define void @async_load_async_wait() #0 { ret void }
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attributes #0 = { "amdgpu-waves-per-eu"="1,1" }
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...
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---
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name: tensor_load_tensor_load
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tracksRegLiveness: true
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body: |
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bb.0:
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; DEFAULT-LABEL: name: tensor_load_tensor_load
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; DEFAULT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: S_ENDPGM 0
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_256 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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TENSOR_LOAD_TO_LDS_d2 %0:sgpr_128, %1:sgpr_256, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2 %0:sgpr_128, %1:sgpr_256, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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S_ENDPGM 0
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...
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---
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name: tensor_wait_tensor_load
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tracksRegLiveness: true
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body: |
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bb.0:
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; DEFAULT-LABEL: name: tensor_wait_tensor_load
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; DEFAULT: S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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; DEFAULT-NEXT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: S_ENDPGM 0
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_256 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2 %0:sgpr_128, %1:sgpr_256, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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S_ENDPGM 0
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...
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---
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name: tensor_wait_tensor_wait
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tracksRegLiveness: true
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body: |
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bb.0:
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; DEFAULT-LABEL: name: tensor_wait_tensor_wait
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; DEFAULT: S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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; DEFAULT-NEXT: S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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; DEFAULT-NEXT: dead [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; DEFAULT-NEXT: dead [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: S_ENDPGM 0
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_256 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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S_ENDPGM 0
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...
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---
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name: tensor_load_tensor_wait
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tracksRegLiveness: true
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body: |
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bb.0:
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; DEFAULT-LABEL: name: tensor_load_tensor_wait
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; DEFAULT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; DEFAULT-NEXT: TENSOR_LOAD_TO_LDS_d2 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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; DEFAULT-NEXT: S_ENDPGM 0
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_256 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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TENSOR_LOAD_TO_LDS_d2 %0:sgpr_128, %1:sgpr_256, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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S_WAIT_TENSORCNT 3, implicit-def dead $tensorcnt, implicit $tensorcnt
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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S_ENDPGM 0
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...
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---
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name: async_load_async_load
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tracksRegLiveness: true
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body: |
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bb.0:
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; DEFAULT-LABEL: name: async_load_async_load
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; DEFAULT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR [[DEF]], [[DEF1]], [[DEF4]], 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR [[DEF]], [[DEF1]], [[DEF4]], 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: SCHED_GROUP_BARRIER 32, 1, 0
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; DEFAULT-NEXT: SCHED_GROUP_BARRIER 2, 6, 0
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; DEFAULT-NEXT: S_ENDPGM 0
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sreg_64 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32 = IMPLICIT_DEF
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GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR %0:vgpr_32, %1:sreg_64, %4:vgpr_32, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR %0:vgpr_32, %1:sreg_64, %4:vgpr_32, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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SCHED_GROUP_BARRIER 32, 1, 0
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SCHED_GROUP_BARRIER 2, 6, 0
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S_ENDPGM 0
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...
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---
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name: async_wait_async_load
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tracksRegLiveness: true
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body: |
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bb.0:
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; DEFAULT-LABEL: name: async_wait_async_load
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; DEFAULT: S_WAIT_ASYNCCNT 2, implicit-def dead $asynccnt, implicit $asynccnt
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; DEFAULT-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
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; DEFAULT-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; DEFAULT-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR [[DEF]], [[DEF1]], [[DEF4]], 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; DEFAULT-NEXT: S_ENDPGM 0
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sreg_64 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32 = IMPLICIT_DEF
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S_WAIT_ASYNCCNT 2, implicit-def dead $asynccnt, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR %0:vgpr_32, %1:sreg_64, %4:vgpr_32, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
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S_ENDPGM 0
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...
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---
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name: async_wait_async_wait
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tracksRegLiveness: true
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body: |
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|
bb.0:
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; DEFAULT-LABEL: name: async_wait_async_wait
|
|
; DEFAULT: S_WAIT_ASYNCCNT 2, implicit-def dead $asynccnt, implicit $asynccnt
|
|
; DEFAULT-NEXT: S_WAIT_ASYNCCNT 1, implicit-def dead $asynccnt, implicit $asynccnt
|
|
; DEFAULT-NEXT: dead [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: dead [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: S_ENDPGM 0
|
|
%0:vgpr_32 = IMPLICIT_DEF
|
|
%1:sreg_64 = IMPLICIT_DEF
|
|
%2:vgpr_32 = IMPLICIT_DEF
|
|
%3:vgpr_32 = IMPLICIT_DEF
|
|
%4:vgpr_32 = IMPLICIT_DEF
|
|
S_WAIT_ASYNCCNT 2, implicit-def dead $asynccnt, implicit $asynccnt
|
|
S_WAIT_ASYNCCNT 1, implicit-def dead $asynccnt, implicit $asynccnt
|
|
%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
---
|
|
name: async_load_async_wait
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
; DEFAULT-LABEL: name: async_load_async_wait
|
|
; DEFAULT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; DEFAULT-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR [[DEF]], [[DEF1]], [[DEF4]], 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_4:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: dead [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF2]], [[DEF3]], implicit $exec
|
|
; DEFAULT-NEXT: SCHED_GROUP_BARRIER 32, 1, 0
|
|
; DEFAULT-NEXT: SCHED_GROUP_BARRIER 2, 6, 0
|
|
; DEFAULT-NEXT: S_WAIT_ASYNCCNT 2, implicit-def dead $asynccnt, implicit $asynccnt
|
|
; DEFAULT-NEXT: S_ENDPGM 0
|
|
%0:vgpr_32 = IMPLICIT_DEF
|
|
%1:sreg_64 = IMPLICIT_DEF
|
|
%2:vgpr_32 = IMPLICIT_DEF
|
|
%3:vgpr_32 = IMPLICIT_DEF
|
|
%4:vgpr_32 = IMPLICIT_DEF
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B64_SADDR %0:vgpr_32, %1:sreg_64, %4:vgpr_32, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
S_WAIT_ASYNCCNT 2, implicit-def dead $asynccnt, implicit $asynccnt
|
|
%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%4:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%5:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%6:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%7:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
%8:vgpr_32 = V_ADD_U32_e32 %2, %3, implicit $exec
|
|
SCHED_GROUP_BARRIER 32, 1, 0
|
|
SCHED_GROUP_BARRIER 2, 6, 0
|
|
S_ENDPGM 0
|
|
...
|
|
|